SEC2410 datasheet(75/283 Pages) MICROCHIP

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 2013 - 2014 Microchip Technology Inc.

DS00001587C-page 75

SEC2410/SEC4410

10.8.2

WDT CONTROL REGISTER

10.8.3

WDT KICK REGISTER

10.8.4

WDT COUNT REGISTER

TABLE 10-5:

WDT CONTROL REGISTER

WDT_CTL

(ADDR 0XF00404, RESET=0X00)

Watch Dog Timer Control Register

Bit

Name

R/W

Description

7:5

Reserved

Always read ‘0’

JTAG_STALL_EN

R/W

This bit is used to enable the JTAG_ACTIVE (JTAG_RST# pin not

asserted) WDT STALL Operation on page 73.

0= JTAG_ACTIVE WDT STALL Operation not enabled

1= JTAG_ACTIVE WDT STALL Operation enabled

WT_STALL_EN

R/W

Firmware must always set this bit to ‘0’.

HT_STALL_EN

R/W

Firmware must always set this bit to ‘0’.

WDT_STATUS

R/W

WDT_STATUS is set by hardware if the last reset of

SEC2410/SEC4410 was caused by an underflow of the WDT. See

Section 10.6.3, "WDT Reload Mechanism," on page 73 for more

information.

This bit must be cleared by the EC firmware writing a ‘1’ to this bit.

Writing a ‘0’ to this bit has no effect

WDT_ENABLE

R/W

The default of the WDT is inactive.

In WDT Operation, the WDT is activated by the sequence of

operations defined in Section 10.6.1, "WDT Activation Mechanism"

and deactivated by the sequence of operations defined in Section

10.6.2, "WDT Deactivation Mechanism". In WDT STALL Operation,

hardware may be enabled to automatically activate and deactivate the

WDT.

TABLE 10-6:

WDT KICK REGISTER

WDT_KICK

(ADDR 0XF00408, RESET=NA)

Watch Dog Timer Kick Register

Bit

Name

R/W

Description

7:0

KICK

This register is a strobe. Reads of this register return 0.

Writes to this register cause the WDT to reload the WDT_LOAD value

and start decrementing when the WDT_ENABLE bit in the WDT_CTL

writes to this register have no effect.

TABLE 10-7:

WDT COUNT REGISTER

WDT_COUNT

(ADDR 0XF0040C, RESET=0XFFFF)

Watch Dog Count Register

Bit

Name

R/W

Description

15:0

WDT_COUNT

This register provide the current WDT count

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