SEC2410 datasheet(97/283 Pages) MICROCHIP

97 / 283 page

 2013 - 2014 Microchip Technology Inc.

DS00001587C-page 97

SEC2410/SEC4410

FORCE_CE

R/W

When this bit is set, it forces the SPI chip enable low. This bit should

only be set when using the SPI command buffer. It should never be

set when doing direct accesses from the AHB bus.

DUAL_OUT_EN

R/W

0:Dual output disabled for fast reads

1:Dual output enabled for fast reads.

MODE_SEL

R/W

This set the SPI clock mode

0: Mode 0

1: Mode 3

CACHE_EN

R/W

Enable the SPI cache

R/W

This is a self clearing bit. Setting this bit will cause the SPI transaction

to initiate.

TABLE 12-3:

SPI COMMAND LENGTH REGISTER

SPI_CMD_LEN

(0X0001 - RESET=0X00)

SPI Command Length

Bit

Name

R/W

Description

7:0

CMD_LEN[7:0]

R/W

This is the length of the SPI transaction length for firmware initiated

transactions.

TABLE 12-4:

SPI TRACE FIFO OPCODE

SPI_TF_OPCODE

(0X0002 - RESET=0X00)

SPI Trace FIFO Opcode

Bit

Name

R/W

Description

7:0

TF_OPCODE

R/W

This is the opcode used when the processor does a write to

0x6100BFFE or 0x6100BFFF. Use the value of 0xDB

TABLE 12-5:

FAST READ OPCODE

SPI_FR_OPCODE

(0X0003 - RESET=0X0B)

SPI Fast Read Opcode

Bit

Name

R/W

Description

7:0

FR_OPCODE

R/W

This is the opcode used when the processor does a fast read

0x0B: Single output read

0x3B: Dual output read

TABLE 12-6:

SPI COMMAND BUFFER

SPI_CMD_BUF

(0X0008~0X000F - RESET=0X00)

SPI Command Buffer

Byte

Name

R/W

Description

7:0

SPI_CMD_BUF[0:7]

R/W

This buffer is used by processor to store outgoing SPI commands.

See behavioral description.

Note:

First byte to go out is SPI_CMD_BUF[0] at offset location 0x0008.

TABLE 12-2:

SPI MODE CONTROL REGISTER (CONTINUED)

SPI_CTL

(0X0000 - RESET=0X02)

SPI Mode Control

Bit

Name

R/W

Description

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