SEC2410 datasheet(64/283 Pages) MICROCHIP

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SEC2410/SEC4410

DS00001587C-page 64

 2013 - 2014 Microchip Technology Inc.

9.6.5

INTERRUPT IDENTIFICATION REGISTER (IIR)

By accessing this register, the CPU can determine the highest priority interrupt and its source. Four levels of priority

interrupt exist. They are in descending order of priority:

Receiver Line Status (highest priority)

Received Data Ready

Transmitter Holding Register Empty

MODEM Status (lowest priority)

Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Iden-

tification Register (refer to Table 9-11). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indi-

cates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new

interrupts, the current indication does not change until access is completed. The contents of the IIR are described below.

TABLE 9-10:

UART INTERRUPT IDENTIFICATION REGISTER(IIR)

UART_IIR (DLAB=X)

(OFFSET 0X02 RESET=0X01)

UART Interrupt Identification Register

Bit

Name

R/W

Description

7:6

FIFO_EN

These two bits are set when the FIFO CONTROL Register bit 0

equals 1

5:4

Reserved

Always read ‘0’

3:1

INTLD

These three bits of the IIR are used to identify the highest priority

interrupt pending as indicated by Table 9-11. In non-FIFO mode, Bit[3]

is a logic “0”. In FIFO mode Bit[3] is set along with Bit[2] when a

timeout interrupt is pending.

IPEND

This bit can be used in either a hardwired prioritized or polled

environment to indicate whether an interrupt is pending. When bit 0 is

a logic "0", an interrupt is pending and the contents of the IIR may be

used as a pointer to the appropriate internal service routine. When bit

0 is a logic "1", no interrupt is pending.

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