SEC2410 datasheet(32/283 Pages) MICROCHIP

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SEC2410/SEC4410

DS00001587C-page 32

 2013 - 2014 Microchip Technology Inc.

4.9

Arbitration

The Processor Memory Complex (PMC) consists of the three memories, namely the ROM, IRAM, DRAM. The ICode

bus is a read only bus which can access ROM, IROM. The DCode and AHB bus have read access to ROM, IRAM,

DRAM, and write access to IRAM, DRAM.

The arbitration priority is fixed and is shown in table below. For each bus, the accesses are always in order of commands

received. This module can be modified for other arbitration schemes. Currently only fixed arbitration is supported. The

highest priority is the DCode bus, since any wait states in the data bus access stall the processor pipeline. The next

highest priority is the ICode bus. The last priority is the AHB bus.

4.10

ICode Bus Interface

The ICode bus supports only IDLE/NSEQ type read accesses which are SINGLE and 32-bit wide. There are no bursts,

and master BSY operation is not supported. The hproti protection information is not used.

Typically, the address from the ICode bus is registered by the ROM/IRAM at the rising edge of hclk, and the read data

from the ROM/IRAM in the next clock is routed combinatorially to the ICode bus.

If there is no contention of access to IROM/IRAM, then back to back reads are executed in zero wait state.

The ARM Cortex-M3 processor matches the AMBA 3 specification except for maintaining control information during

waited transfers. The processor might change the access type from SEQ or NONSEQ to IDLE during a waited transfer

(hreadyi is low). In effect this cancels the outstanding transfer that has not yet occurred because the previous access is

wait-stated and awaiting completion. This enables the processor to have a lower interrupt latency and higher perfor-

mance in wait-stated systems. The ICode bus interface logic ignores such aborted outstanding reads.

4.11

DCode Bus Interface

The DCode bus supports IDLE/NSEQ/SEQ type accesses, which may be SINGLE or INCR bursts. The data width may

be byte/Half-word/Word accesses. Master BSY operation and Locked accesses are not supported. The hprotd protec-

tion information is not used.

TABLE 4-3:

MEMORY ACCESS TYPE

Memory

ICode Access

DCode Access

AHB Access

ROM

RRR

IRAM

DRAM

None

TABLE 4-4:

MEMORY ACCESS PRIORITY

Priority

Bus Access

ROM

DCode (R)

ICode (R)

3AHB (R)

IRAM

DCode (RW)

ICode (R)

3AHB (RW)

DRAM

DCode (RW)

2AHB (RW)

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