SEC2410 datasheet(90/283 Pages) MICROCHIP

90 / 283 page

SEC2410/SEC4410

DS00001587C-page 90

 2013 - 2014 Microchip Technology Inc.

12.0

SPI CONTROLLER

12.1

Overview

The SPI controller has three basic modes of operation. When operating as a memory bus to a SPI ROM, it takes System

AMBA bus accesses in the range 0x6000_0000 through 0x60FF_FFFF (16MBytes), and convert them to SPI ROM

accesses, construct the data, and provide data back to the ARM along with the ready signal at the appropriate time.

In parallel with SPI ROM reading hardware is a 32 byte cache that keeps track of data that has been fetched.

The second mode of operation is for all SPI operations that are not fast reads or Trace FIFO accesses. In this mode,

the firmware is responsible for setting up a command buffer, and control registers. The firmware then fires the command

by setting a ‘GO’ bit. The firmware is also responsible for parsing the response from the SPI slave. These registers exist

in the range of 0x6100_0000 to 0x6100_03FF.

The last mode of operation is for debugging. The firmware writes to System AHB addresses 0x6100BFFE and

0x6100BFFF to send out trace message to Microchip’s trace FIFO board. The SPI controller sends out accesses to

these locations as special messages that are ignored by the SPI ROM, but are intercepted by the debugging hardware.

The SPI interface is always enabled after reset. It can be disabled by setting the SPI_DISABLE bit in the UTIL_CON-

FIG1 register.

12.2

DEVICE OPERATION INSTRUCTIONS

There is only one operation supported automatically in hardware: FAST_READ. All instructions associated with Auto-

matic Address Increment (AAI) are supported. Everything else is handled through firmware intervention.

TABLE 12-1:

SPI OPCODES

Instruction

Description

OP Code

Cycle

Address

Cycle(s)

Dummy

Cycle(s)

Data

Cycle(s)

Total

Resp

WRSR

Write Status Register

0x01

Byte_program

To program one Data

Byte

0x02

READ

Read Slow Mode

0x03

1 to

5 to ¥

N/A

WRDI

Write Disable

0x04

RDSR

Read Status Register

0x05

1 to

2 to

WREN

Write Enable

0x06

FAST_READ

Read Fast Mode

0x0B

1 to

6 to

SCTR_ERASE

4 KByte Sector Erase

0x20

0xD7

DUAL

FAST_READ

Dual Read Fast Mode 0x3B

1 to

6 to

EWSR

Enable Write Status

0x50

32BLK_ERASE

32 KByte Block Erase 0x52

CHIP_ERASE

Erase full memory

array

0x60

0xC7

EBSY

Enable SO to output

Busy during AAI

programming

0x70

N/A

DBSY

Disable SO to output

Busy during AAI

programming

0x80

N/A

RDID

Read ID

0x90

1 to

5 to

JEDEC_ID

JEDEC ID read

0x9F

3 to

4 to

RDCR

Read Config Register

0xA1

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