SEC2410 datasheet(59/283 Pages) MICROCHIP

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DS00001587C-page 59

SEC2410/SEC4410

9.1.3

BLOCK DIAGRAM SIGNAL LIST

9.1.4

TRANSMIT OPERATION

Transmission is initiated by writing the data to be sent to the TX Holding Register or to the TX FIFO (if enabled). The

data is then transferred to the TX Shift Register together with a start bit and parity and stop bits as determined by settings

in the Line Control Register. The bits to be transmitted are then shifted out of the TX Shift Register in the order Start bit,

Data bits (LSB first), Parity bit, Stop bit, using the output from the Baud Rate Generator (divided by 16) as the clock.

If enabled, a TX Holding Register Empty interrupt will be generated when the TX Holding Register or the TX FIFO (if

enabled) becomes empty.

When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the M16550S can store up to 16 bytes of data

for transmission at a time. Transmission will continue until the TX FIFO is empty. The FIFO’s readiness to accept more

data is indicated by interrupt.

9.1.5

RECEIVE OPERATION

Data is sampled into the RX Shift Register using the Receive clock, divided by 16. The Receive clock is provided either

by the Baud Rate Generator. A filter is used to remove spurious inputs that last for less than two periods of the Receive

clock. When the complete word has been clocked into the receiver, the data bits are transferred to the RX Buffer Reg-

ister or to the RX FIFO (if enabled) to be read by the CPU. (The first bit of the data to be received is placed in bit 0 of

this register.) The receiver also checks that the parity bit and stop bits are as specified by the Line Control Register.

If enabled, an RX Data Received interrupt will be generated when the data has been transferred to the RX Buffer Reg-

ister or, if FIFOs are enabled, when the RX Trigger Level has been reached. Interrupts can also be generated to signal

RX FIFO Character Timeout, incorrect parity, a missing stop bit (frame error) or other Line Status errors.

When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the M16550S can store up to 16 bytes of

received data at a time. Depending on the selected RX Trigger Level, interrupt will go active to indicate that data is avail-

able when the RX FIFO contains 1, 4, 8 or 14 bytes of data.

9.2

Power, Clocks and Reset

9.2.1

POWER

This block is only active if UART_POWER_EN is set to a ‘1’ in DEV_CLK_EN register, otherwise this block is disabled

and the clocks are shut off.

9.2.2

CLOCKS

The MCLK used for the logic in this block is 60Mhz. The UART_CLK is sourced from either a 24MHz or 16MHz clock.

The two different clocks are required to ensure a sub 1% error for 50baud to 2Mbaud. In order to maintain communica-

tion with acceptable error, an accurate baud clock is required. The clock is selected using the BAUD_CLK_SEL bit in

UART_CTL register.

TABLE 9-1:

SERIAL PORT (UART) REGISTER INTERFACE PORT LIST

Signal Name

Direction

Description

nRESET

input

HW reset

CLK

Input

Block operating clock

EC IF

I/O Bus

Bus used for register access

UART_INT

Output

Host Interrupt

UART_CLK_24MHz

Input

24MHz UART clock.

UART_CLK_16MHz

Input

16MHz UART clock.

UART_TX

Output

UART Transmit data pin

UART_RX

Input

UART Receive data pin

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