SEC2410 datasheet(91/283 Pages) MICROCHIP

91 / 283 page

 2013 - 2014 Microchip Technology Inc.

DS00001587C-page 91

SEC2410/SEC4410

Note 1:

One bus cycle is eight clock periods.

Address bits above the most significant bit of each density should be set to 0x00.

12.3

Operation of the Hi-Speed Read Sequence

The SPI controller handles code reads going out to the SPI ROM Address automatically. When the controller detects a

read, the controller drops the SPI_CE, and puts out a 0x0B, followed by the 24-bit address. The SPI controller then puts

out a DUMMY byte. The next eight clocks clock in the first byte. When the first byte is clocked in a ready signal is sent

back to the processor, and the processor gets one byte.

After the processor gets the first byte, its address will change. If the address is one more than the last address, the SPI

controller will clock out one more byte. If the address in anything other than one more than the last address, the SPI

controller will terminate the transaction by taking SPI_CE high. As long as the addresses are sequential, the SPI Con-

troller will keep clocking in data.

12.4

Operation of the Dual Hi-Speed Read Sequence

The SPI controller also supports dual data mode. When configured in dual mode, the SPI controller will automatically

handle reads going out to the SPI ROM. When the controller detects a read, the controller drops the SPI_CEN, and puts

out a 0x3B (the value must be programmed into the SPI_ FR_OPCODE Register), followed by the 24-bit address. The

SPI controller then puts out a DUMMY byte. The next four clocks clock in the first byte. The data appears two bits at a

time on data out and data in. When the first byte is clocked in a ready signal is sent back to the processor, and the pro-

cessor gets one byte.

RDES

Read Electronic

Signature

0xAB

1 to

5 to

AAI_PROGRAM Auto Address

Increment

programming

0xAD

2 to

6 to

N/A

64BLK_ERASE

64 KByte Block Erase 0xD8

WRCR

Write Config Register

0xF1

FIGURE 12-1:

SPI HI-SPEED READ SEQUENCE

TABLE 12-1:

SPI OPCODES (CONTINUED)

Instruction

Description

OP Code

Cycle

Address

Cycle(s)

Dummy

Cycle(s)

Data

Cycle(s)

Total

Resp

SPI_CEN

SPI_CLK

SPI_DO

SPI_DI

MSB

HIGH IMPEDANCE

15 16

12 3 4

DOUT

ADD.

23 24

ADD.

39 40

31 32

47 48

55 56

63 64

71 72

DOUT

NN+1

DOUT

N+2

DOUT

N+3

DOUT

N+4

MSB

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