SEC2410 datasheet(69/283 Pages) MICROCHIP

69 / 283 page

 2013 - 2014 Microchip Technology Inc.

DS00001587C-page 69

SEC2410/SEC4410

9.6.9

MODEM STATUS REGISTER (MSR)

This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to

this current state information, four bits of the MODEM Status Register (MSR) provide change information.

These bits are set to logic "1" whenever a control input from the MODEM changes state. They are reset to logic "0"

whenever the MODEM Status Register is read.

Note 9-10

Whenever bit 0, 1, 2, or 3 is set to a logic "1", a MODEM Status Interrupt is generated.

APPLICATION NOTE: The Modem Status Register (MSR) only provides the current state of the UART MODEM

control lines in Loopback Mode. The SEC2410/SEC4410 does not support external

connections for the MODEM Control inputs (nCTS, nDSR, nRI and nDCD) or for the four

MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2).

OVERRUN_ERROR

Overrun Error. Bit 1 indicates that data in the Receiver Buffer Register

was not read before the next character was transferred into the

overrun error will occur only when the FIFO is full and the next

character has been completely received in the shift register, the

character in the shift register is overwritten but not transferred to the

FIFO. The OE indicator is set to a logic "1" immediately upon

detection of an overrun condition, and reset whenever the Line Status

DATA_READY

Data Ready. It is set to a logic "1" whenever a complete incoming

character has been received and transferred into the Receiver Buffer

data in the Receive Buffer Register or the FIFO

TABLE 9-16:

UART MODEM STATUS REGISTER(MSR)

UART_MSR (DLAB=X)

(OFFSET 0X06 RESET=0BXXXX0000)

UART Modem Status Register

Bit

Name

R/W

Description

DCD#

This bit is the complement of the Data Carrier Detect (nDCD) input. If

bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT2 in

the MCR.

RI#

This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of

the MCR is set to logic "1", this bit is equivalent to OUT1 in the MCR.

DSR

This bit is the complement of the Data Set Ready (nDSR) input. If bit

4 of the MCR is set to logic "1", this bit is equivalent to DTR in the

MCR.

CTS

This bit is the complement of the Clear To Send (nCTS) input. If bit 4

of the MCR is set to logic "1", this bit is equivalent to nRTS in the

MCR.

DDCD

Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input

to the chip has changed state.

TERI

Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI

input has changed from logic "0" to logic "1".

DDSR

Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input

has changed state since the last time the MSR was read.

DCTS

Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to

the chip has changed state since the last time the MSR was read.

TABLE 9-15:

UART LINE STATUS REGISTER(MCR) (CONTINUED)

UART_LINE_STAT (DLAB=X)

(OFFSET 0X05 RESET=0X60)

UART Line Status Register

Bit

Name

R/W

Description

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