SEC2410 datasheet(61/283 Pages) MICROCHIP

61 / 283 page

 2013 - 2014 Microchip Technology Inc.

DS00001587C-page 61

SEC2410/SEC4410

Note 9-1

DLAB is Bit 7 of the Line Control Register.

9.5

TABLE 9-4:

TWO PIN SERIAL PORT (UART) REGISTER SUMMARY

DLAB

(Note 9-1)

EC_SPB Interface

Notes

Offset address

Byte

Lane

EC Type

Receive Buffer Register (RB),

0x00

Transmit Buffer Register (TB)

0x00

The incoming clock is divided by the

value held in DLL & DLM (1 - 65535)

to produce the Baud Rate Generator

Output signal (BAUD)

0x00

R/W

The incoming clock is divided by the

value held in DLL & DLM (1 - 65535)

to produce the Baud Rate Generator

Output signal (BAUD)

0x01

R/W

Interrupt Enable Register (IER)

0x01

R/W

FIFO Control Register (FCR),

0x02

Interrupt Identification Register (IIR)

0x02

Line Control Register (LCR)

0x03

R/W

Modem Control Register (MCR)

0x04

R/W

Line Status Register (LSR)

0x05

Modem Status Register (MSR)

0x06

Scratchpad Register (SCR)

0x07

R/W

N/A

EC INTERFACE

OFFSET

ADDRESS

BYTE

LANE

EC TYPE

UART Control Register

0x10

R/W

TABLE 9-5:

Address

(Note 9-2)R/W

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADDR = 0

DLAB = 0

Receive Buffer r

Data Bit 7

Data Bit 6

Data Bit 5

Data Bit 4

Data Bit 3

Data Bit 2

Data Bit 1

Data Bit 0

(Note 9-3)

ADDR = 0

DLAB = 0

Transmitter Holding r

Data Bit 7

Data Bit 6

Data Bit 5

Data Bit 4

Data Bit 3

Data Bit 2

Data Bit 1

Data Bit 0

ADDR = 1

DLAB = 0

R/W

Interrupt Enable r

Reserved

Enable

Modem

Status

Interrupt

(EMSI)

Enable

Receiver

Line Sta-

tus Inter-

rupt (ELSI)

Enable

Trans-mit-

ter Holding

Empty

Interrupt

(ETHREI)

Enable

Received

Data Avail-

able Inter-

rupt

(ERDAI)

ADDR = 2

Interrupt Ident. r

FIFOs

Enabled

(Note 9-7)

FIFOs

Enabled

(Note 9-7)

Reserved

Interrupt ID

Bit (Note 9-

Interrupt ID

Bit

Interrupt ID

Bit

"0" if Inter-

rupt Pend-

ing

ADDR = 2

FIFO Control r

RCVR Trig-

ger MSB

RCVR Trig-

ger LSB

Reserved

DMA Mode

Select

(Note 9-8)

XMIT FIFO

Reset

RCVR

FIFO

Reset

FIFO

Enable

ADDR = 3

R/W

Line Control r

Divisor

Latch

Access Bit

(DLAB)

Set Break

Stick Parity

Even Parity

Select

(EPS)

Parity

Enable

(PEN)

Number of

Stop Bits

(STB)

Word

Length

Select Bit 1

(WLS1)

Word

Length

Select Bit 0

(WLS0)

ADDR = 4

R/W

MODEM Control r

Reserved

Loop

OUT2

(Note 9-5)

OUT1

(Note 9-5)

Request to

Send

(RTS)

Data Ter-

minal

Ready

(DTR)

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