SEC2410 datasheet(73/283 Pages) MICROCHIP

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DS00001587C-page 73

SEC2410/SEC4410

10.4

Clocks

This block has two clock inputs, the EC_CLK and CLK. The EC_CLKis used in the interface to the embedded controller

accessible registers. The 32.768KHz CLK is the clock source for the Watchdog Timer functional logic, including the

counter.

10.5

WDT Event output

In the SEC2410/SEC4410, the assertion of the WDT Event output causes a Watch-Dog Timer Forced Reset.

The WDT Event state is also retained through a Watch-Dog Timer Forced Reset in the WD_RESET bit of Reset control

The WDT Event output is not directly connected to an EC interrupt.

10.6

WDT Operation

10.6.1

WDT ACTIVATION MECHANISM

The WDT is activated by the following sequence of operations during normal operation:

Load the WDT Load Register with the count value.

Set the WDT Enable bit in the WDT Control Register.

The WDT Activation Mechanism starts the WDT decrementing counter.

10.6.2

WDT DEACTIVATION MECHANISM

The WDT is deactivated by the clearing the WDT Enable bit in the WDT Control Register. The WDT Deactivation Mech-

anism places the WDT in a low power state in which clock are gated and the counter stops decrementing.

10.6.3

WDT RELOAD MECHANISM

The WDT must be reloaded within periods that are shorter than the programmed watchdog interval; otherwise the WDT

will underflow and a WDT Event will be generated and the WDT_STATUS bit will be set in the WDT Control Register. It

is the responsibility of the user program to continually execute sections of code which reload the watchdog timer (WDT)

causing the counter to be reloaded

There are two methods of reloading the WDT: a write to the WDT Kick Register or the WDT Activation Mechanism.

10.6.4

WDT INTERVAL

The WDT Interval is the time it takes for the WDT to decrements from the WDT Load Register value to 0000h. The WDT

Count Register value takes 1.007ms to decrement by 1 count.

10.6.5

WDT STALL OPERATION

The WDT has several events that can cause the WDT STALL. When a WDT STALL event is asserted, the WDT stops

decrementing, and the WDT enters a low power state. When a WDT STALL event is de-asserted, the counter is

reloaded with the programmed preload value and starts decrementing.

The WDT STALL feature has been implemented for convenience. If the system designer chooses not to utilize the WDT

STALL feature, the WDT defaults with the WDT STALL feature disabled.

There are three Stall inputs to the WDT: HT_ACTIVE, WT_ACTIVE, JTAG_ACTIVE (corresponding to the Hibernation

Timer, the Week Alarm Timer, & the J-TAG interface being active). The Stall inputs have individual enable bits:

HT_STALL_EN, WT_STALL_EN, JTAG_STALL_EN bits in the Table 10-5, “WDT Control Register,” on page 75.

EC_IF

I/O Bus

Bus used by microprocessor to access the registers in this block.

EC_CLK

INPUT

Clock used to access internal register.

WDT Event

OUTPUT

Pulse generated when WDT expires.

TABLE 10-1:

WATCHDOG TIMER INTERFACE SIGNAL LIST (CONTINUED)

Signal Name

Direction

Description

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