SEC2410 datasheet(92/283 Pages) MICROCHIP

92 / 283 page

SEC2410/SEC4410

DS00001587C-page 92

 2013 - 2014 Microchip Technology Inc.

After the processor gets the first byte, the address will change. If the address is one more than the last address, the SPI

controller will clock out one more byte. If the address in anything other than one more than the last address, the SPI

controller will terminate the transaction by taking SPI_CE high. As long as the addresses are sequential, the SPI Con-

troller will keep clocking in data.

12.5

32 Byte Cache

There is a 32-byte pipeline cache, and associated with the cache is a base address pointer and a length pointer. Once

the SPI controller detects a jump, the base address pointer is initialized to that address. As each new sequential data

byte is fetched, the data is written into the cache, and the length is incremented. If the sequential run exceeds 32 bytes,

the base address pointer is incremented to indicate the last 32 bytes fetched. If the SEC2410/SEC4410 does a jump,

and the jump is in the cache address range, the fetch is done in 1 clock from the internal cache instead of an external

access.

12.6

Interface Operation to SPI Port When Not Doing Fast Reads

There is an 8-byte command buffer: SPI_CMD_BUF[7:0]; an 8-byte response buffer: SPI_RESP_BUF[7:0]; and a length

D_LEN X 8 number of clocks. After the first byte, the COMMAND, has been sent out, and the SPI_DI is stored in the

SPI_RESP buffer. If the SPI_CMD_LEN is longer than the SPI_CMD_BUF, don’t cares are sent out on the SPI_DO line.

This mode is used for program execution out of internal RAM or ROM.

12.6.1

ERASE EXAMPLE

To perform a SCTR_ERASE, 32BLK_ERASE, or 64BLK_ERASE, the SEC2410/SEC4410 writes 0x20, 0x52, or 0xD8,

respectively to the first byte of the command buffer, followed by a 3-byte address. The length of the transfer is set to 4

bytes. To do this, the SEC2410/SEC4410 first drops SPI_CE, then counts out 8 clocks. It then puts out the 8 bits of

command, followed by 24 bits of address of the location to be erased on the SPI_DO pin. When the transfer is complete,

the SPI_CEN goes high, while the SPI_DI line is ignored in this example.

FIGURE 12-2:

SPI DUAL HI-SPEED READ SEQUENCE

SPI_CEN

SPI_CLK

SPI_DO

SPI_DI

MSB

HIGH IMPEDANCE

15 16

12 3 4

ADD.

23 24

ADD.

39 40

31 32

47 48

51 52

55 56

NN+1

N+2

N+3

N+4

MSB

N+1

N+2

N+3

N+4

MSB

Bits-7,5,3,1

Bits-6,4,2,0

Bits-7,5,3,1

Bits-6,4,2,0

SEC2410 Datasheet(PDF) 92 Page - Microchip Technology

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