SEC2410 datasheet(101/283 Pages) MICROCHIP

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DS00001587C-page 101

SEC2410/SEC4410

may be controlled by software to initiate these sequences. When either of these resets terminates (SC_RST_N going

high) the Smart Card will return a sequence of characters called the "Answer to Reset" or "ATR" message as defined

by ISO 7816-3. The smart card is required to respond to a reset sequence as shown in the Cold Reset and Warm Reset

timing diagrams (see Figure 13-8 and Figure 13-9).

The first character of the ATR message, called "TS", is interpreted by hardware in SEC2410/SEC4410, determining the

bit encoding convention used by the card (Direct or Inverse) as defined by ISO 7816-3, which defines the polarity and

the order of the Data and Parity bits in the character. The TS byte, interpreted according to the convention it selects, is

placed into the FIFO, and data received from that point onward is assembled according to the selected convention and

loaded into the FIFO to be read by software.

The rest of the ATR response from the Smart Card returns the operational limits of the Smart Card. Software must inter-

pret this response and set the SEC2410/SEC4410 runtime registers accordingly. During the ATR message, data will be

received based on a default value of the bit time, called the Elementary Time Unit, abbreviated as “etu”. Two ATR param-

eters named F and D are used to define a new etu time. Once this is determined, software can program the BRG Divisor

and the sampling rate for the Baud Rate generator accordingly. The hardware divides the 60MHz system clock, by the

BRG Divisor and the sampling rate to determine the etu value (bit time). The SC_CLK frequency is generated by dividing

the System clock by the SC_CLK_DIV DIVISOR field. Software will also set up the Extra Guard Time register (EGT),

the Block Guard Time (BGT) register and the protocol mode ("T=0" or "T=1" mode) to set the required amount of guard

time between character transmissions.

A negotiation phase called PPS may occur, or communication may begin immediately using the parameters provided

by the card’s ATR message. In either case, all communication after the ATR message consists of individual

“exchanges”, in which the IFD transmits a block of data and the ICC responds with a return message. For this reason,

and because the response time from the ICC can be too short for software intervention, software will enable both the

SEC2410/SEC4410 transmitter and receiver at the same time, and the receiver hardware will remain inactive until the

transmission phase of the exchange has completed.

An additional “Stop Clock” feature has been provided to hold the SC_CLK output at a particular voltage level between

exchanges, as may be allowed by the card for power savings. Clock switching is glitch free.

Hardware protocol timers, set according to default timings, will monitor the Smart Card interface during the Reset/ATR

sequence for an unresponsive or defective card, based on the EMV, ISO and PC/SC timing requirements. If the ATR

response is not received within the given time, or does not obey the required timings, a timer interrupt will result, and

the software can take corrective action or initiate the deactivation sequence to stop and power-down the card.

After the ATR sequence, the same set of hardware timers are used, based on ATR parameters EGT, CWT, BWT, and/or

WWT, to monitor timings for the subsequent data exchanges.

One of two protocols is selected, defined by a parameter T in the ATR message, and potentially negotiated in a PPS

exchange. The protocol “T=0” is character-oriented, with parity error detection and re-transmission on a character-by-

character basis. The protocol “T=1” is block-oriented, with an error-free link layer based on block re-transmission,

resembling the X.25 communication standard. In the T=1 protocol, both individual character parity and a block check

field are used to detect errors.

The SEC2410/SEC4410 FIFO is deep enough to hold an entire message of maximum length (259 bytes). It transmits

data, pre-loaded into the FIFO, when the Transmit control bit is set by software. It immediately turns around, enabling

the receiver to put data received back into the FIFO. The FIFO threshold interrupt is triggered by received data only,

though a separate interrupt is available to signal when the Transmit phase has ended. The hardware has significant

knowledge of the protocol being implemented, and can be set up to filter out bytes that would lead to a message longer

than the FIFO depth.

13.4

Character Framing

The SEC2410/SEC4410 meets the requirements for a character frame as defined by ISO 7816-3. The T=0 and T=1

protocol differ in the minimum amount of Guard Time: 2 etus for T=0, and 1 etu for T=1, which does not require a char-

acter-by-character Parity Error response.

Character parity is checked as each byte is received by hardware. If a parity error is detected when a byte is received,

the Parity Error status bit will be set. This status bit can be polled by software, or it can be programmed to generate an

interrupt and/or to deactivate the card in hardware. If character repetition is enabled (used in the T=0 protocol) the

SEC2410/SEC4410 will pull the SC_IO line low following a received parity error, for the duration of 1 etu as defined by

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