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SEC2410 Datasheet(PDF) 104 Page - Microchip Technology |
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SEC2410 Datasheet(HTML) 104 Page - Microchip Technology |
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104 / 283 page ![]() SEC2410/SEC4410 DS00001587C-page 104 2013 - 2014 Microchip Technology Inc. 13.5.3 RECOMMENDED ETU RATES AND SETTINGS Table 13-2 lists the valid etu rates supported, and the recommended settings of the DL Divisor (in the DLL/DLM regis- ters) and the Sampling field of the CLK register that are used to select them. If the sampling clock is set to 01, then the baud rate is simply calculated by: BAUD_RATE = SYSTEM_FREQUENCY / ( DL_DIVISOR) Where: SYSTEM_FREQUENCY = 60,000,000 and DL = The concatenation of SC_DLM with SC_DLL TABLE 13-2: RECOMMENDED SETTINGS FOR VALID TA1 ETU RATES FI (Dec) DI (Dec) Sampling Field (Binary) SCLK (Actual) MHz DL Divisor Value (Decimal) Baud Rate (Bits/Sec) Error (%) Notes 0 1 00 4 180 10753 0 2 00 4 90 21505 0 3 00 4 45 43011 0 4 01 4 698 86022 0.07 0 5 01 4 349 172043 0.07 0 6 01 4 174 344086 0.22 0 7 01 4 87 688172 0.22 0 8 00 4 465 129032 0 9 01 4 279 215054 1 1 10 5 279 13441 1 2 01 5 2232 26882 1 3 01 5 1116 53763 1 4 01 5 558 107527 1 5 01 5 279 215054 1 6 01 5 140 430108 0.36 1 7 01 5 70 860215 0.36 1 8 01 5 372 161290 1 9 01 5 223 268817 0.09 2 1 00 6 180 10753 2 2 00 6 90 21505 2 3 01 6 1395 43011 2 4 01 6 689 86022 0.07 2 5 01 6 349 172043 0.07 2 6 01 6 174 344086 0.22 2 7 01 6 87 688172 0.22 2 8 01 6 465 129032 2 9 01 6 279 215054 3 1 00 7.5 192 10753 3 2 00 7.5 96 21505 3 3 00 7.5 48 43011 3 4 00 7.5 24 86022 3 5 01 7.5 372 172043 3 6 01 7.5 186 344086 3 7 01 7.5 93 688172 3 8 00 7.5 16 129032 |
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