AD6674 datasheet(60/91 Pages) AD

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AD6674

Data Sheet

ADC

SYSREF±

SYNCINB±

CONVERTER A

INPUT

CONVERTER B

INPUT

CONVERTER 0

CONVERTER 1

SERDOUT0–,

SERDOUT0+

SERDOUT1–,

SERDOUT1+

SERDOUT2–,

SERDOUT2+

SERDOUT3–,

SERDOUT3+

LANE MUX

AND MAPPING

(SPI

REG 0x5B0,

REG 0x5B2,

REG 0x5B3,

REG 0x5B5,

REG 0x5B6)

JESD204B LINK

CONTROL

(L, M, F)

(SPI REG 0x570)

MUX/

FORMAT

(SPI

REG 0x561,

REG 0x564)

NOISE

SHAPING

REQUANTIZER

NOISE

SHAPING

REQUANTIZER

Figure 120. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x200 = 0x07)

JESD204B SAMPLE

CONSTRUCTION

SERDOUT0±

SERDOUT1±

TAIL BITS

REG 0x571[6]

FRAME

CONSTRUCTION

SCRAMBLER

1 +

x14 + x15

(OPTIONAL)

8B/10B

ENCODER

SERIALIZER

ADC

ADC TEST PATTERNS

(REG 0x550,

REG 0x551 TO REG 0x558)

JESD204B LONG

TRANSPORT TEST

PATTERN

REG 0x571[5]

JESD204B DATA

LINK LAYER TEST

PATTERNS

REG 0x574[2:0]

MSB

LSB

SYMBOL0

SYMBOL1

A13

A12

A11

A10

A13

A12

A11

A10

MSB

LSB

MSB

LSB

b c d e f g h i

a b . . . .

. . . .

a b

a b c d e f g h i

CONTROL BITS

JESD204B

INTERFACE TEST

PATTERNS

(REG 0x573,

REG 0x551 TO REG 0x558)

Figure 121. ADC Output Datapath Showing Data Framing

TRANSPORT

LAYER

PHYSICAL

LAYER

DATA LINK

LAYER

OUTPUT

SAMPLE

CONSTRUCTION

FRAME

CONSTRUCTION

SCRAMBLER

ALIGNMENT

CHARACTER

GENERATION

8-BIT/10-BIT

ENCODER

CROSSBAR

MUX

SERIALIZER

PROCESSED

SAMPLES

FROM ADC

SYSREF±

SYNCINB±

Figure 122. Data Flow

FUNCTIONAL OVERVIEW

The block diagram in Figure 122 shows the flow of data through

the JESD204B hardware from the sample input to the physical

output. The processing can be divided into layers that are derived

from the open-source initiative (OSI) model that is widely used

to describe the abstractions layers of communications systems.

These are the transport layer, data link layer, and physical layer

(serializer and output driver).

Transport Layer

The transport layer packs the data (consisting of samples and

optional control bits) into JESD204B frames, which are mapped

to 8-bit octets that are sent to the data link layer. The transport

layer mapping is controlled by rules derived from the link

parameters. Tail bits are added to fill gaps where required. Use

the following equation to determine the number of tail bits

within a sample (JESD204B word):

T = N΄ − N − CS

Data Link Layer

The data link layer is responsible for the low level functions of

passing data across the link. These include optionally

scrambling the data, inserting control characters for multichip

synchronization/lane alignment/monitoring, and encoding

8-bit octets into 10-bit symbols. The data link layer is also

responsible for sending the ILAS, which contains the link

configuration data, used by the receiver to verify the settings in

the transport layer.

Physical Layer

The physical layer consists of the high speed circuitry clocked at

the serial clock rate. In this section, parallel data is converted

into one, two, or four lanes of high speed differential serial data.

JESD204B LINK ESTABLISHMENT

The AD6674 JESD204B Tx interface operates in Subclass 1 as

defined in the JEDEC Standard No. 204B (July 2011) specification.

The link establishment process is divided into the following

steps: code group synchronization, ILAS, and user data.

Rev. B | Page 60 of 91

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