AD6674 datasheet(72/91 Pages) AD

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AD6674

Data Sheet

Rev. B | Page 72 of 91

TEST MODES

ADC TEST MODES

The AD6674 has various test options that aid in the system level

implementation. The AD6674 has ADC test modes that are

available in Register 0x550. These test modes are described in

Table 38. When an output test mode is enabled, the analog

section of the ADC is disconnected from the digital back-end

blocks and the test pattern is run through the output formatting

block. Some of the test patterns are subject to output formatting,

and some are not. The PN generators from the PN sequence

tests can be reset by setting Bit 4 or Bit 5 of Register 0x550.

These tests can be performed with or without an analog signal

(if present, the analog signal is ignored), but they do require an

encode clock. For more information, see the AN-877 Application

Note, Interfacing to High Speed ADCs via SPI.

JESD204B BLOCK TEST MODES

In addition to the ADC test modes, the AD6674 also has flexible

test modes in the JESD204B block. These test modes are listed

in Register 0x573 and Register 0x574. These test patterns can be

inserted at various points along the output data path. These test

insertion points are shown in Figure 121. Table 39 describes the

various test modes available in the JESD204B block. For the

AD6674, a transition from the test modes (Register 0x573 ≠

0x00) to normal mode (0x573 = 0x00) require a SPI soft reset.

This is done by writing 0x81 to Register 0x00 (self cleared).

Transport Layer Sample Test Mode

The transport layer samples are implemented in the AD6674 as

defined by Section 5.1.6.3 in the JEDEC JESD204B specification.

These tests are enabled via Register 0x571[5]. The test pattern is

equivalent to the raw samples from the ADC.

Interface Test Modes

The interface test modes are described in Register 0x573, Bits[3:0].

These test modes are also explained in Table 39. The interface

tests can be inserted at various points along the data. See Figure 121

for more information on the test insertion points. Register 0x573,

Bits[5:4], show where these tests are inserted.

Table 38. ADC Test Modes

Output Test Mode

Bit Sequence

Pattern Name

Expression

Default/Seed

Value

Sample (N, N + 1, N + 2, …)

0000

Off (default)

Not applicable

0001

Midscale short

00 0000 0000 0000

Not applicable

0010

+Full-scale short

01 1111 1111 1111

Not applicable

0011

−Full-scale short

10 0000 0000 0000

Not applicable

0100

Checkerboard

10 1010 1010 1010

Not applicable

0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555

0101

PN sequence long

x23 + x18 + 1

0x3AFF

0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6

0110

PN sequence short

x9 + x5 + 1

0x0092

0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697

0111

One-/zero word

toggle

11 1111 1111 1111

Not applicable

0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000

1000

User input

Not applicable

For repeat mode: User Pattern 1[15:2], User Pattern 2[15:2],

User Pattern 3[15:2], User Pattern 4[15:2], User Pattern 1[15:2]…

For single mode: User Pattern 1[15:2], User Pattern 2[15:2],

User Pattern 3[15:2], User Pattern 4[15:2], 0x0000…

1111

Ramp output

(x) % 214

Not applicable

(x) % 214, (x + 1) % 214, (x + 2) % 214, (x + 3) % 214

Table 39. JESD204B Interface Test Modes

Output Test Mode

Bit Sequence

Pattern Name

Expression

Default

0000

Off (default)

Not applicable

0001

Alternating checker board

0x5555, 0xAAAA, 0x5555…

Not applicable

0010

1/0 word toggle

0x0000, 0xFFFF, 0x0000…

Not applicable

0011

31-bit PN sequence

x31 + x28 + 1

0x0003AFFF

0100

23-bit PN sequence

x23 + x18 + 1

0x003AFF

0101

15-bit PN sequence

x15 + x14 + 1

0x03AF

0110

9-bit PN sequence

x9 + x5 + 1

0x092

0111

7-bit PN sequence

x7 + x6 + 1

0x07

1000

Ramp output

(x) % 216

Ramp size depends on test insertion point

1110

Continuous/repeat user test

User Pattern 1 to User Pattern 4, then repeat

1111

Single user test

User Pattern 1 to User Pattern 4, then zeros

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