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AD6674 Datasheet(PDF) 84 Page - Analog Devices |
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AD6674 Datasheet(HTML) 84 Page - Analog Devices |
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84 / 91 page ![]() AD6674 Data Sheet Reg. Addr. (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes 0x375 DDC 3 frequency MSB X X X X DDC3 NCO FTW[11:8] twos complement 0x00 0x380 DDC 3 phase LSB DDC3 NCO POW[7:0] twos complement 0x00 0x381 DDC 3 phase MSB X X X X DDC3 NCO POW[11:8] twos complement 0x00 0x387 DDC 3 output test mode selection 0 0 0 0 0 Q output test mode enable 0 = disabled 1 = enabled from Ch. B 0 I output test mode enable 0 = disabled 1 = enabled from Ch. A 0x00 NSR Decimate by 2 and Noise Shaping Requantizer (NSR) 0x41E NSR decimate by 2 High- pass/ low-pass mode: 0 = enable LPF 1 = enable HPF X 0 0 X X X NSR decimate by 2 enable 0 = disabled 1 = enabled 0x01; 0x00 for AD6674 -500 Bit 0 is ignored on AD6674 -750 and AD6674 -1000 when in NSR mode 0x420 NSR mode X X X X NSR mode 000 = 21% BW mode 001 = 28% BW mode X 0x00 0x422 NSR tuning X X NSR tuning word; see the Noise Shaping Requantizer (NSR) section; equations for the tuning word are dependent on the NSR mode 0x00 Variable Dynamic Range (VDR) 0x430 VDR control X X X 0 X X VDR BW mode 0 = 25% BW mode 1 = 43% BW mode (only available for dual complex mode) 0 = dual real mode 1 = dual complex mode (Channel A = I, Channel B = Q) 0x01 0x434 VDR tuning X X X X VDR center frequency; see the Variable Dynamic Range (VDR) section for more details on the center frequency, which is dependent on the VDR mode 0x00 Digital Outputs and Test Modes 0x550 ADC test modes (local) User pattern selection 0 = contin- uous repeat 1 = single pattern 0 Reset PN long gen 0 = long PN enable 1 = long PN reset Reset PN short gen 0 = short PN enable 1 = short PN reset Test mode selection 0000 = off (normal operation) 0001 = midscale short 0010 = positive full scale 0011 = negative full scale 0100 = alternating checker board 0101 = PN sequence, long 0110 = PN sequence, short 0111 = 1/0 word toggle 1000 = user pattern test mode (used with Register 0x550, Bit 7, and User Pattern 1 to User Patten 4 registers) 1111 = ramp output 0x00 Rev. B | Page 84 of 91 |
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