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AD6674 Datasheet(PDF) 87 Page - Analog Devices |
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AD6674 Datasheet(HTML) 87 Page - Analog Devices |
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87 / 91 page  Data Sheet AD6674 Reg. Addr. (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes 0x571 JESD204B Link Mode Control 1 Standby mode 0 = all con- verter outputs 0 1 = CGS (K28.5) Tail bit (T) PN 0 = disable 1 = enable T = N’ − N − CS Long trans- port layer test 0 = disable 1 = enable Lane synchron- ization 0 = disable FACI uses /K28.7/ 1 = enable FACI uses /K28.3/ and /K28.7/ ILAS sequence mode 00 = ILAS disabled 01 = ILAS enabled 11 = ILAS always on test mode Frame align- ment character insertion (FACI) 0 = enabled 1 = disabled Link control 0 = active 1 = power down 0x14 0x572 JESD204B Link Mode Control 2 SYNCINB± pin control 00 = normal 10 = ignore SYNCINB± (force CGS) 11 = ignore SYNCINB± (force ILAS/user data) SYNCINB± pin invert 0 = active low 1 = active high SYNCINB± pin type 0 = differential 1 = CMOS 0 8B/10B bypass 0 = normal 1 = bypass 8B/10B bit invert 0 = normal 1 = invert abcde fghij symbols 0 0x00 0x573 JESD204B Link Mode Control 3 CHKSUM mode 00 = sum of all 8-bit link configuration registers 01 = sum of individual link configuration fields 10 = checksum set to zero Test insertion point 00 = N’ sample input 01 = 10-bit data at 8B/10B output (for PHY testing) 10 = 8-bit data at scrambler input JESD204B test mode patterns 0000 = normal operation (test mode disabled) 0001 = alternating checker board 0010 = 1/0 word toggle 0011 = 31-bit PN sequence—x31 + x28 + 1 0100 = 23-bit PN sequence—x23 + x18 + 1 0101 = 15-bit PN sequence—x15 + x14 + 1 0110 = 9-bit PN sequence—x9 + x5 + 1 0111 = 7-bit PN sequence—x7 + x6 + 1 1000 = ramp output 1110 = continuous/repeat user test 1111 = single user test 0x00 0x574 JESD204B Link Mode Control 4 ILAS delay 0000 = transmit ILAS on first LMFC after SYNCINB± deasserted 0001 = transmit ILAS on second LMFC after SYNCINB± deasserted … 1111 = transmit ILAS on 16th LMFC after SYNCINB± deasserted 0 Link layer test mode 000 = normal operation (link layer test mode disabled) 001 = continuous sequence of /D21.5/ characters 100 = modified RPAT test sequence 101 = JSPAT test sequence 110 = JTSPAT test sequence 0x00 0x578 JESD204B LMFC offset 0 0 0 LMFC Phase Offset Value[4:0] 0x00 0x580 JESD204B DID config JESD204B Tx DID Value[7:0] 0x00 0x581 JESD204B BID config 0 0 0 0 JESD204B Tx BID Value[3:0] 0x00 0x583 JESD204B LID Config 1 0 0 0 Lane 0 LID Value[4:0] 0x00 0x584 JESD204B LID Config 2 0 0 0 Lane 1 LID Value[4:0] 0x01 0x585 JESD204B LID Config 3 0 0 0 Lane 2 LID Value[4:0] 0x01 0x586 JESD204B LID Config 4 0 0 0 Lane 3 LID Value[4:0] 0x03 0x58B JESD204B parameters (SCR/L) JESD204B scram- bling (SCR) 0 = disabled 1 = enabled 0 0 0 0 0 JESD204B lanes (L) 00 = 1 lane 01 = 2 lanes 11 = 4 lanes read only; see Register 0x570 0x83 Rev. B | Page 87 of 91 |
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