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AD6674 Datasheet(PDF) 69 Page - Analog Devices

Part # AD6674
Description  385 MHz BW IF Diversity Receiver
PDF  91 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6674 Datasheet(HTML) 69 Page - Analog Devices

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Data Sheet
AD6674
YES
UPDATE
SETUP/HOLD
DETECTOR STATUS
(0x128)
INCREMENT
SYSREF± IGNORE
COUNTER
YES
NO
SYSREF±
ENABLED?
(0x120)
NO
CLOCK
DIVIDER
> 1?
(0x10B)
YES
NO
INPUT
CLOCK
DIVIDER
ALIGNMENT
REQUIRED?
YES
NO
NO
YES
ALIGN CLOCK
DIVIDER
PHASE TO
SYSREF±
SYNCHRONIZATION
MODE?
(0x1FF)
TIMESTAMP
MODE
NORMAL
MODE
YES
SYSREF±
INSERTED
IN JESD204B
CONTROL BITS
BACK TO START
NO
DDC NCO
ALIGNMENT
ENABLED?
(0x300)
YES
NO
NO
YES
SEND K28.5
CHARACTERS
NORMAL
JESD204B
INITIALIZATION
SYSREF±
CONTROL BITS?
(0x559, 0x55A,
0x58F)
RESET
SYSREF± IGNORE
COUNTER
NO
START
SYSREF±
ASSERTED?
YES
NO
YES
ALIGN SIGNAL
MONITOR
COUNTERS
YES
NO
NO
YES
NO
INCREMENT
SYSREF±
COUNTER
(0x12A)
SYSREF±
TIMESTAMP
DELAY
(0x123)
BACK TO START
SYSREF±
IGNORE
COUNTER
EXPIRED?
(0x121)
CLOCK
DIVIDER
AUTO ADJUST
ENABLED?
(0x10D)
RAMP
TEST
MODE
ENABLED?
(0x550)
SYSREF± RESETS
RAMP TEST
MODE
GENERATOR
JESD204B
LMFC
ALIGNMENT
REQUIRED?
ALIGN PHASE
OF ALL
INTERNAL CLOCKS
(INCLUDING LMFC)
TO SYSREF±
SEND INVALID
8B/10B
CHARACTERS
(ALL 0s)
SYNC~
ASSERTED
SIGNAL
MONITOR
ALIGNMENT
ENABLED?
(0x26F)
ALIGN DDC
NCO PHASE
ACCUMULATOR
Figure 139. Multichip Synchronization
Rev. B | Page 69 of 91



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