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AD6674

Data Sheet

Table 9. Differential Transformer Coupled Input Configuration Component Values

Device

Frequency Range

Transformer

R1 (Ω)

R2 (Ω)

R3 (Ω)

C1 (pF)

C2 (pF)

AD6674-500

DC to 250 MHz

ETC1-1-13

250 MHz to 2 GHz

BAL0006/BAL0006SMG

AD6674-750

DC to 375 MHz

ETC1-1-13

375 MHz to 2 GHz

BAL0006/BAL0006SMG

AD6674-1000

DC to 500 MHz

ECT1-1-13/BAL0006SMG

500 MHz to 2 GHz

BAL0006/BAL0006SMG

Open

Input Common Mode

The analog inputs of the AD6674 are internally biased to the

common mode, as shown in Figure 72. The common-mode

buffer has limited range in that the performance suffers greatly

if the common-mode voltage drops by more than 100 mV.

Therefore, in dc-coupled applications, set the common-mode

voltage to 2.05 V ± 100 mV to ensure proper ADC operation.

Analog Input Controls and SFDR Optimization

The AD6674 offers flexible controls for the analog inputs such

as input termination, input capacitance, buffer current, and

input full-scale adjustment. All of the available controls are

shown in Figure 72.

10pF

VIN+x

VIN–x

AVDD3

VCM

BUFFER

400Ω

AVDD3

1.5pF

3pF

1.5pF

3pF

AIN CONTROL

SPI REGISTERS

(0x008, 0x015,

0x016, 0x018,

0x019, 0x01A,

0x11A, 0x934,

0x935)

Figure 72. Analog Input Controls

Use Register 0x018, Register 0x019, Register 0x01A, Register 0x11A,

each channel to optimize the SFDR over various input frequencies

and bandwidths of interest.

Input Buffer Control Registers (Register 0x018, Register

0x019, Register 0x01A, Register 0x934, Register 0x935,

The input buffer has many registers that set the bias currents

and other settings for operation at different frequencies. These

bias currents and settings can be changed to suit the input

frequency range of operation. Register 0x018 controls the buffer

bias current to reduce the effects of charge kickback from the

ADC core. This setting can be scaled from a low setting of 1.0× to

a high setting of 8.5×. The default setting in Register 0x018 is

3.0× for the AD6674-750 and AD6674-1000, whereas the

default for the AD6674-500 is 2.0×. These settings are sufficient

for operation in the first Nyquist zone. As the input buffer

currents are set, the amount of current required by the AVDD3

supply changes. This relationship is shown in Figure 73. For a

complete list of buffer current settings, see Table 45 for more

details.

100

150

200

250

300

150

250

350

450

550

650

750

850

BUFFER CURRENT SETTING

AD6674-1000

AND

AD6674-750

AD6674-500

Figure 73. IAVDD3 vs. Buffer Current Setting in Register 0x018

offer secondary bias controls for the input buffer for frequencies

>500 MHz. Register 0x934 can be used to reduce input

capacitance to achieve wider signal bandwidth but doing so

may result in slightly lower linearity and noise performance.

These register settings do not affect the AVDD3 power as much as

recommended to use the default settings for these registers.

Table 10 shows the recommended values for the buffer current

control registers for various speed grades.

Use Register 0x11A when sampling in higher Nyquist zones

(>500 MHz for the AD6674-1000). This setting enables the

ADC sampling network to optimize the sampling and settling

times internal to the ADC for high frequency operation. For

frequencies greater than 500 MHz, it is recommended to

operate the ADC core at a 1.46 V full-scale setting irrespective

of the speed grade. This setting offers better SFDR without any

significant decrease in SNR.

Figure 74, Figure 75, and Figure 76 show the SFDR vs. analog input

frequency for various buffer settings (IBUFF) for the AD6674-1000.

Rev. B | Page 26 of 91

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