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AD6674

Data Sheet

8B/10B Encoder

The 8B/10B encoder converts 8-bit octets into 10-bit symbols

and inserts control characters into the stream when needed.

The control characters used in JESD204B are shown in Table 33.

The 8B/10B encoding ensures that the signal is dc balanced by

using the same number of ones and zeros across multiple symbols.

The 8B/10B interface has options that can be controlled via the

SPI. These operations include bypass and invert. These options

are intended to be a troubleshooting tool for the verification of

the digital front end (DFE). Refer to the Memory Map section,

encoder.

PHYSICAL LAYER (DRIVER) OUTPUTS

Digital Outputs, Timing and Controls

The AD6674 physical layer consists of drivers that are defined

in the JEDEC Standard No. 204B (July 2011). The differential

digital outputs are powered up by default. The drivers use a

dynamic 100 Ω internal termination to reduce unwanted

reflections.

Place a 100 Ω differential termination resistor at each receiver

input, which results in a nominal 300 mV p-p swing at the

receiver (see Figure 124). Alternatively, single-ended 50 Ω

termination resistors can be used. When single-ended

termination is used, the termination voltage is DRVDD/2;

otherwise, 0.1 μF ac coupling capacitors can be used to

terminate to any single-ended voltage.

SERDOUTx+

DRVDD

VRXCM

SERDOUTx–

OUTPUT SWING = 300mV p-p

0.1µF

100Ω

50Ω

0.1µF

RECEIVER

VCM = VRXCM

100Ω

DIFFERENTIAL

TRACE PAIR

Figure 124. AC-Coupled Digital Output Termination Example

The AD6674 digital outputs can interface with custom ASICs

and FPGA receivers, providing superior switching performance

in noisy environments. Single point-to-point network topologies

are recommended with a single differential 100 Ω termination

resistor placed as close to the receiver inputs as possible. The

common mode of the digital output automatically biases itself

to half the DRVDD supply of 1.2 V (VCM = 0.6 V). See Figure 125

for an example of dc coupling the outputs to the receiver logic.

SERDOUTx+

DRVDD

SERDOUTx–

OUTPUT SWING = 300mV p-p

100Ω

RECEIVER

VCM = DRVDD/2

100Ω

DIFFERENTIAL

TRACE PAIR

Figure 125. DC-Coupled Digital Output Termination Example

If there is no far-end receiver termination, or if there is poor

differential trace routing, timing errors may result. To avoid

such timing errors, it is recommended that the trace length be

less than six inches, and that the differential output traces be

close together and at equal lengths.

Figure 126 to Figure 128, Figure 129 to Figure 131, and Figure 132

to Figure 134 show examples of the digital output data eye, time

interval error (TIE) jitter histogram, and bathtub curve for one

AD6674 lane running at 10 Gbps, 7.37 Gbps, and 6 Gbps,

respectively. The format of the output data is twos complement

by default. To change the output data format, see the Memory

Map section (Register 0x561 in Table 45).

De-Emphasis

De-emphasis enables the receiver eye diagram mask to be met

in conditions where the interconnect insertion loss does not

meet the JESD204B specification. Use the de-emphasis feature

only when the receiver is unable to recover the clock due to

excessive insertion loss. Under normal conditions, it is disabled

to conserve power. Additionally, enabling and setting too high a

de-emphasis value on a short link may cause the receiver eye

diagram to fail. Use the de-emphasis setting with caution

because it may increase EMI. See the Memory Map section

(Register 0x5C1 to Register 0x5C5 in Table 45) for more

information.

PLL

The PLL is used to generate the serializer clock, which operates

at the JESD204B lane rate. The JESD204B lane rate control bit

(Register 0x56E[4]) must be set to correspond with the lane rate.

Rev. B | Page 62 of 91

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