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AD6674 Datasheet(PDF) 66 Page - Analog Devices

Part # AD6674
Description  385 MHz BW IF Diversity Receiver
PDF  91 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6674 Datasheet(HTML) 66 Page - Analog Devices

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AD6674
Data Sheet
Table 36. JESD204B Output Configurations for N΄ = 8
Number of Virtual
Converters Supported
(Same Value as M)
JESD204B Quick
Configuration
(Register 0x570)
Serial Lane Rate1
JESD204B Transport Layer Settings2
L
M
F
S
HD
N
N΄
CS
K3
1
0x00
10 × fOUT
1
1
1
1
0
7 to 8
8
0 to 1
Only valid K
values that
are divisible
by 4 are
supported
0x01
10 × fOUT
1
1
2
2
0
7 to 8
8
0 to 1
0x40
5 × fOUT
2
1
1
2
0
7 to 8
8
0 to 1
0x41
5 × fOUT
2
1
2
4
0
7 to 8
8
0 to 1
0x42
5 × fOUT
2
1
4
8
0
7 to 8
8
0 to 1
0x80
2.5 × fOUT
4
1
1
4
0
7 to 8
8
0 to 1
0x81
2.5 × fOUT
4
1
2
8
0
7 to 8
8
0 to 1
2
0x09
20 × fOUT
1
2
2
1
0
7 to 8
8
0 to 1
0x48
10 × fOUT
2
2
1
1
0
7 to 8
8
0 to 1
0x49
10 × fOUT
2
2
2
2
0
7 to 8
8
0 to 1
0x88
5 × fOUT
4
2
1
2
0
7 to 8
8
0 to 1
0x89
5 × fOUT
4
2
2
4
0
7 to 8
8
0 to 1
0x8A
5 × fOUT
4
2
4
8
0
7 to 8
8
0 to 1
1
fOUT is the output sample rate. fOUT = ADC sample rate/chip decimation. The JESD204B serial lane rate must be ≥3.125 Gbps and ≤12.5 Gbps; when the serial lane rate is
≤12.5 Gbps and ≥6.25 Gbps, the low lane rate mode must be disabled (set Bit 4 to 0x0 in Register 0x56E). When the serial lane rate is <6.25 Gbps and ≥3.125 Gbps, the
low lane rate mode must be enabled (set Bit 4 to 0x1 in Register 0x56E).
2
JESD204B transport layer descriptions are as described in the JESD204B Overview section.
3
For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32.
Example 1: ADC with DDC Option (Two ADCs + Four DDCs)
The chip application mode is four-DDC mode (see Figure 137)
with the following characteristics:
•
Two 14-bit converters at 1 GSPS
•
Four DDCs application layer mode with complex outputs
(I/Q)
•
Chip decimation ratio = 16
•
DDC decimation ratio = 16 (see Table 15)
The JESD204B output configuration is as follows:
•
Virtual converters required = 8 (see Table 35)
•
Output sample rate (fOUT) = 1000/16 = 62.5 MSPS
Supported JESD204B output configurations (see Table 35)
include
•
N΄ = 16 bits
•
N = 14 bits
•
L = 1, M = 8, and F = 16; or L = 2, M = 8, and F = 8 (quick
configuration = 0x1C or 0x5B)
•
CS = 0 to 1
•
K = 32
•
Output serial lane rate = 10 Gbps per lane (L = 1) or
5 Gbps per lane (L = 2)
•
For L = 1, low lane rate mode disabled
•
For L = 2, low lane rate mode enabled
Example 1 shows the flexibility in the digital and lane
configurations for the AD6674. The sample rate is 1 GSPS, but
the outputs are all combined into either one or two lanes
depending on the I/O speed capability of the receiving device.
Example 2: ADC with NSR Option (Two ADCs + NSR)
The chip application mode is NSR mode (see Figure 138) with
the following characteristics:
•
Two 14-bit converters at 500 MSPS
•
NSR blocks enabled for each channel
•
Chip decimation ratio = 1
The JESD204B output configuration is as follows:
•
Virtual converters required = 2 (see Table 35)
•
Output sample rate (fOUT) = 500 MSPS
Supported JESD204B output configurations (see Table 35)
include
•
N΄ = 16 bits
•
N = 9 bits
•
L = 2, M = 2, and F = 2; L = 4, M = 2, and F = 1 (quick
configuration = 0x49 or 0x88)
•
CS = 0 to 2
•
K = 32
•
Output serial lane rate = 10 Gbps per lane (L = 2) or
5 Gbps per lane (L = 4)
•
For L = 2, low lane rate mode disabled
•
For L = 4, low lane rate mode enabled
Example 2 shows the flexibility in the digital and lane
configurations for the AD6674. The sample rate is 500 MSPS,
but the outputs are all combined into either two or four lanes
depending on the I/O speed capability of the receiving device.
Rev. B | Page 66 of 91



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