AD6674 datasheet(90/91 Pages) AD

90 / 91 page

AD6674

Data Sheet

Rev. B | Page 90 of 91

APPLICATIONS INFORMATION

POWER SUPPLY RECOMMENDATIONS

The AD6674 must be powered by the following seven supplies:

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR

= 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V.

For applications requiring an optimal high power efficiency and

low noise performance, it is recommended that the ADP2164

and ADP2370 switching regulators be used to convert the 3.3 V,

5.0 V, or 12 V input rails to an intermediate rail (1.8 V and

3.8 V). These intermediate rails are then postregulated by very

low noise, low dropout (LDO) regulators (ADP1741, ADM7172,

and ADP125). Figure 142 shows the recommended method. For

more detailed information on the recommended power

solution, refer to the AD6674 evaluation board documentation.

AVDD1

1.25V

AVDD1_SR

1.25V

DVDD

1.25V

SPIVDD

(1.8V OR 3.3V)

3.6V

3.3V

DRVDD

1.25V

1.8V

ADP1741

ADP125

AVDD3

3.3V

ADM7172

ADP1741

AVDD2

2.5V

ADP1741

Figure 142. High Efficiency, Low Noise Power Solution for the AD6674

It is not necessary to split all of these power domains in all

cases. The recommended solution shown in Figure 142 provides

the lowest noise, highest efficiency power delivery system for

the AD6674. If only one 1.25 V supply is available, it must be

routed to AVDD1 first and then tapped off and isolated with a

ferrite bead or a filter choke preceded by decoupling capacitors

for AVDD1_SR, DVDD, and DRVDD, in that order. The user

can use several different decoupling capacitors to cover both

high and low frequencies. These must be located close to the

point of entry at the PCB level and close to the devices, with

minimal trace lengths.

EXPOSED PAD THERMAL HEAT SLUG

RECOMMENDATIONS

It is required that the exposed pad on the underside of the ADC

be connected to ground to achieve the best electrical and

thermal performance of the AD6674. Connect an exposed

continuous copper plane on the PCB to the AD6674 exposed

pad, Pin 0. The copper plane must have several vias to achieve

the lowest possible resistive thermal path for heat dissipation to

flow through the bottom of the PCB. These vias must be solder

filled or plugged. The number of vias and the fill determine the

resultant θJA measured on the board.

To maximize the coverage and adhesion between the ADC and

PCB, partition the continuous copper plane by overlaying a

silkscreen on the PCB into several uniform sections. This

provides several tie points between the ADC and PCB during

the reflow process, whereas using one continuous plane with no

partitions only guarantees one tie point. See Figure 143 for a

PCB layout example. For detailed information on packaging

and the PCB layout of chip scale packages, see the AN-772

Application Note, A Design and Manufacturing Guide for the

Lead Frame Chip Scale Package (LFCSP).

Figure 143. Recommended PCB Layout of Exposed Pad for the AD6674

AVDD1_SR (PIN 57) AND AGND (PIN 56, PIN 60)

AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) can be

used to provide a separate power supply node to the SYSREF±

circuits of the AD6674. If running in Subclass 1, the AD6674

can support periodic one-shot or gapped signals. To minimize

the coupling of this supply into the AVDD1 supply node,

adequate supply bypassing is needed.

AD6674 Datasheet(PDF) 90 Page - Analog Devices

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