WM5102 datasheet(104/334 Pages) WOLFSON

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WM5102

Production Data

PD, June 2014, Rev 4.2

104

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3584

(0E00h)

FX_Ctrl

15:12

FX_RATE [3:0]

0000

FX Sample Rate (EQ, LHPF, DRC)

0000 = SAMPLE_RATE_1

0001 = SAMPLE_RATE_2

0010 = SAMPLE_RATE_3

1000 = ASYNC_SAMPLE_RATE_1

1001 = ASYNC_SAMPLE_RATE_2

All other codes are Reserved.

The selected sample rate is valid in the

range 8kHz to 192kHz.

When the DRC is enabled, the maximum

FX_RATE sample rate is 96kHz.

R4352

(1100h)

DSP1

Control 1

15:12

DSP1_RATE [3:0]

0000

DSP1 Sample Rate

0000 = SAMPLE_RATE_1

0001 = SAMPLE_RATE_2

0010 = SAMPLE_RATE_3

1000 = ASYNC_SAMPLE_RATE_1

1001 = ASYNC_SAMPLE_RATE_2

All other codes are Reserved.

The selected sample rate is valid in the

range 4kHz to 192kHz.

Table 21 Digital Core Sample Rate Control

ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC)

The WM5102 supports multiple signal paths through the digital core. Two independent clock domains

are supported, referenced to SYSCLK and ASYNCCLK respectively, as described in “Clocking and

Sample Rates”. Every digital signal path must be synchronised either to SYSCLK or to ASYNCCLK.

The Asynchronous Sample Rate Converter (ASRC) provides two stereo signal paths between the

SYSCLK and ASYNCCLK domains, as illustrated in Figure 40.

The sample rate on the SYSCLK domain is selected using the ASRC_RATE1 register - the rate can

be set equal to SAMPLE_RATE_1, SAMPLE_RATE_2 or SAMPLE_RATE_3.

The sample rate on the ASYNCCLK domain is selected using the ASRC_RATE2 register - the rate

can be set equal to ASYNC_SAMPLE_RATE_1 or ASYNC_SAMPLE_RATE_2.

See “Clocking and Sample Rates” for details of the sample rate control registers.

The ASRC supports sample rates in the range 8kHz to 48kHz only. The applicable SAMPLE_RATE_n

and ASYNC_SAMPLE_RATE_n registers must each select sample rates between 8kHz and 48kHz

when any ASRC path is enabled.

The ASRC1 Left and ASRC1 Right paths convert from the SYSCLK domain to the ASYNCCLK

domain. These paths are enabled using the ASRC1L_ENA and ASRC1R_ENA register bits

respectively.

The ASRC2 Left and ASRC2 Right paths convert from the ASYNCCLK domain to the SYSCLK

domain. These paths are enabled using the ASRC2L_ENA and ASRC2R_ENA register bits

respectively.

Synchronisation (lock) between different clock domains is not instantaneous when the clocking or

sample rate configurations are updated. The lock status of each ASRC path is an input to the Interrupt

control circuit and can be used to trigger an Interrupt event - see “Interrupts”.

The ASRC Lock status of each ASRC path can be output directly on a GPIO pin as an external

indication of ASRC Lock. See “General Purpose Input / Output” to configure a GPIO pin for this

function.

WM5102 Datasheet(PDF) 104 Page - Wolfson Microelectronics plc

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