WM5102 datasheet(105/334 Pages) WOLFSON

105 / 334 page

Production Data

WM5102

PD, June 2014, Rev 4.2

105

The WM5102 performs automatic checks to confirm that the SYSCLK or ASYNCCLK frequency is

high enough to support the commanded ASRC and digital mixing functions. If an attempt is made to

enable an ASRC signal path, and there are insufficient SYSCLK or ASYNCCLK cycles to support it,

then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be

affected under these circumstances.)

The Underclocked Error can be monitored using the GPIO and/or Interrupt functions. See “General

Purpose Input / Output” and “Interrupts” for further details.

The status bits in Register R3809 indicate the status of each of the ASRC signal paths. If an

Underclocked Error condition occurs, then these bits provide readback of which ASRC signal path(s)

have been successfully enabled.

The status bits in Registers R1600 to R2920 indicate the status of each of the digital mixers. If an

Underclocked Error condition occurs, then these bits provide readback of which mixer(s) have been

successfully enabled.

The Asynchronous Sample Rate Converter (ASRC) signal paths and control registers are illustrated in

Figure 40.

ASRC1R_ENA

ASRC1L_ENA

ASRC1L_SRC

ASRC1R_SRC

ASRC1 Left (90h)

ASRC1 Right (91h)

ASRC2R_ENA

ASRC2L_ENA

ASRC2L_SRC

ASRC2R_SRC

ASRC2 Left (92h)

ASRC2 Right (93h)

ASRC_RATE1

(= SAMPLE_RATE_n)

ASRC_RATE2

(= ASYNC_SAMPLE_RATE_n)

The ASRC provides asynchronous conversion between the SYSCLK and ASYNCCLK CLOCK domains.

ASRC_RATE1 identifies the SYSCLK-related sample rate (SAMPLE_RATE_n).

ASRC_RATE2 identifies the ASYNCCLK-related sample rate (ASYNC_SAMPLE_RATE_n).

Figure 40 Asynchronous Sample Rate Converters (ASRCs)

The ASRC1 and ASRC2 input control registers (see Figure 40) are located at register addresses

R2688 (A80h) through to R2712 (A98h).

The full list of digital mixer control registers is provided in the “Register Map” section (Register R1600

through to R2920). Generic register definitions are provided in Table 7.

The *_SRCn registers select the input source(s) for the respective ASRC processing blocks. Note that

the selected input source(s) must be configured for the same sample rate as the ASRC to which they

are connected.

The bracketed numbers in Figure 40, eg. “(90h)” indicate the corresponding *_SRCn register setting

for selection of that signal as an input to another digital core function.

The register bits associated with the ASRCs are described in Table 22.

WM5102 Datasheet(PDF) 105 Page - Wolfson Microelectronics plc

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