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LAN9250 Datasheet(PDF) 260 Page - Microchip Technology |
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LAN9250 Datasheet(HTML) 260 Page - Microchip Technology |
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260 / 421 page  LAN9250 DS00001913A-page 260 2015 Microchip Technology Inc. 12.2.18.21 PHY Interrupt Mask Register (PHY_INTERRUPT_MASK) This read/write register is used to enable or mask the various PHY interrupts and is used in conjunction with the PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE). Index (decimal): 30 Size: 16 bits Bits Description Type Default 15:10 RESERVED RO - 9 INT9_MASK This interrupt mask bit enables/masks the Link Up (link status asserted) inter- rupt. 0: Interrupt source is masked 1: Interrupt source is enabled R/W 0b 8 RESERVED RO - 7 INT7_MASK This interrupt mask bit enables/masks the ENERGYON interrupt. 0: Interrupt source is masked 1: Interrupt source is enabled R/W 0b 6 INT6_MASK This interrupt mask bit enables/masks the Auto-Negotiation interrupt. 0: Interrupt source is masked 1: Interrupt source is enabled R/W 0b 5 INT5_MASK This interrupt mask bit enables/masks the remote fault interrupt. 0: Interrupt source is masked 1: Interrupt source is enabled R/W 0b 4 INT4_MASK This interrupt mask bit enables/masks the Link Down (link status negated) interrupt. 0: Interrupt source is masked 1: Interrupt source is enabled R/W 0b 3 INT3_MASK This interrupt mask bit enables/masks the Auto-Negotiation LP acknowledge interrupt. 0: Interrupt source is masked 1: Interrupt source is enabled R/W 0b 2 INT2_MASK This interrupt mask bit enables/masks the Parallel Detection fault interrupt. 0: Interrupt source is masked 1: Interrupt source is enabled R/W 0b |
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