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LAN9250 Datasheet(PDF) 256 Page - Microchip Technology |
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LAN9250 Datasheet(HTML) 256 Page - Microchip Technology |
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256 / 421 page  LAN9250 DS00001913A-page 256 2015 Microchip Technology Inc. Note 19: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg- ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY Basic Control Register (PHY_BASIC_CONTROL) is set. Note 20: The default value of this bit is a 1 if in 100BASE-FX mode, otherwise the default is a 0. 3:0 RESERVED RO - TABLE 12-13: AUTO-MDIX ENABLE AND AUTO-MDIX STATE BIT FUNCTIONALITY Auto-MDIX Enable Auto-MDIX State Mode 0 0 Manual mode, no crossover 0 1 Manual mode, crossover 1 0 Auto-MDIX mode 1 1 RESERVED (do not use this state) TABLE 12-14: MDIX STRAP FUNCTIONALITY auto_mdix_strap_1 manual_mdix_strap_1 Mode 0 0 Manual mode, no crossover 0 1 Manual mode, crossover 1 x Auto-MDIX mode Bits Description Type Default |
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