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LAN9250 Datasheet(PDF) 255 Page - Microchip Technology

Part # LAN9250
Description  Integrated Ethernet PHY with HP Auto-MDIX
PDF  421 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9250 Datasheet(HTML) 255 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001913A-page 255
LAN9250
12.2.18.18 PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND)
This read/write register is used to control various options of the PHY.
Index (decimal): 27
Size:
16 bits
Bits
Description
Type
Default
15
Auto-MDIX Control (AMDIXCTRL)
This bit is responsible for determining the source of Auto-MDIX control for the
port. When set, the Manual MDIX and Auto MDIX straps (manual_mdix-
_strap_1/auto_mdix_strap_1) are overridden, and Auto-MDIX functions are
controlled using the AMDIXEN and AMDIXSTATE bits of this register. When
cleared, Auto-MDIX functionality is controlled by the Manual MDIX and Auto
MDIX straps by default. Refer to Section 7.0, "Configuration Straps," on
page 54 for configuration strap definitions.
0: Port Auto-MDIX determined by strap inputs (Table 12-14)
1: Port Auto-MDIX determined by bits 14 and 13
Note:
The value of auto_mdix_strap_1 is indicated in the AMDIX_EN
Strap State bit of the Hardware Configuration Register (HW_CFG).
R/W
NASR
Note 19
0b
14
Auto-MDIX Enable (AMDIXEN)
When the AMDIXCTRL bit of this register is set, this bit is used in conjunction
with the AMDIXSTATE bit to control the Port Auto-MDIX functionality as
shown in Table 12-13.
Auto-MDIX is not appropriate and should not be enabled for 100BASE-FX
mode.
R/W
NASR
Note 19
0b
13
Auto-MDIX State (AMDIXSTATE)
When the AMDIXCTRL bit of this register is set, this bit is used in conjunction
with the AMDIXEN bit to control the Port Auto-MDIX functionality as shown in
Table 12-13.
R/W
NASR
Note 19
0b
12
RESERVED
RO
-
11
SQE Test Disable (SQEOFF)
This bit controls the disabling of the SQE test (Heartbeat). SQE test is
enabled by default.
0: SQE test enabled
1: SQE test disabled
R/W
NASR
Note 19
0b
10:6
RESERVED
RO
-
5
Far End Fault Indication Enable (FEFI_EN)
This bit enables Far End Fault Generation and Detection. See Section
12.2.16.1, "100BASE-FX Far End Fault Indication," on page 229 for more
information.
R/W
Note 20
4
10Base-T Polarity State (XPOL)
This bit shows the polarity state of the 10Base-T.
0: Normal Polarity
1: Reversed Polarity
RO
0b



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