LAN9250 datasheet(252/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 252

 2015 Microchip Technology Inc.

12.2.18.15 PHY TDR Patterns/Delay Control Register (PHY_TDR_PAT_DELAY)

Note 17:

ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the

PHY Basic Control Register (PHY_BASIC_CONTROL) is set.

Index (In Decimal): 24

Size:

16 bits

Bits

Description

Type

Default

TDR Delay In

0 = Line break time is 2 ms.

1 = The device uses

TDR Line Break Counter to increase the line break

time before starting TDR.

R/W

NASR

Note 17

14:12

TDR Line Break Counter

When TDR Delay In is 1, this field specifies the increase in line break time in

increments of 256 ms, up to 2 seconds.

R/W

NASR

Note 17

001b

11:6

TDR Pattern High

This field specifies the data pattern sent in TDR mode for the high cycle.

R/W

NASR

Note 17

101110b

5:0

TDR Pattern Low

This field specifies the data pattern sent in TDR mode for the low cycle.

R/W

NASR

Note 17

011101b

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