LAN9250 datasheet(250/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 250

 2015 Microchip Technology Inc.

12.2.18.14 PHY Special Modes Register (PHY_SPECIAL_MODES)

This read/write register is used to control the special modes of the PHY.

Note 13:

ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the

PHY Basic Control Register (PHY_BASIC_CONTROL) is set.

Note 14:

The default value of this bit is determined by the Fiber Enable strap (fx_mode_strap_1).

Note 15:

The default value of this field is determined by a combination of the configuration straps autoneg_strap_1,

speed_strap_1, and duplex_strap_1. If the autoneg_strap_1 is 1, then the default MODE[2:0] value is 111b.

Else, the default value of this field is determined by the remaining straps. MODE[2]=0,

MODE[1]=(speed_strap_1), and MODE[0]=(duplex_strap_1). Refer to Section 7.0, "Configuration Straps,"

on page 54 for more information. In 100BASE-FX mode, the default value of these bits is 010b or 011b.

depending on the duplex configuration strap.

Note 16:

The default value of this field is determined per Section 12.1.1, "PHY Addressing," on page 210.

Index (decimal): 18

Size:

16 bits

Bits

Description

Type

Default

15:11

RESERVED

100BASE-FX Mode (FX_MODE)

This bit enables 100BASE-FX Mode

Note:

FX_MODE cannot properly be changed with this bit. This bit must

always be written with its current value. Device strapping must be

used to set the desired mode.

R/W

NASR

Note 13

Note 14

9:8

RESERVED

7:5

PHY Mode (MODE[2:0])

This field controls the PHY mode of operation. Refer to Table 12-12 for a defi-

nition of each mode.

Note:

This field should be written with its read value.

R/W

NASR

Note 13

Note 15

4:0

PHY Address (PHYADD)

The PHY Address field determines the MMI address to which the PHY will

respond and is also used for initialization of the cipher (scrambler) key. Refer

to Section 12.1.1, "PHY Addressing," on page 210 for additional information.

R/W

NASR

Note 13

Note 16

TABLE 12-12: MODE[2:0] DEFINITIONS

MODE[2:0]

Mode Definitions

000

10BASE-T Half Duplex. Auto-Negotiation disabled.

001

10BASE-T Full Duplex. Auto-Negotiation disabled.

010

100BASE-TX or 100BASE-FX Half Duplex. Auto-Negotiation disabled. CRS is active

during Transmit & Receive.

011

100BASE-TX or 100BASE-FX Full Duplex. Auto-Negotiation disabled. CRS is active

during Receive.

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