LAN9250 datasheet(364/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 364

 2015 Microchip Technology Inc.

14.8.36

1588 PORT TX TIMESTAMP CONFIGURATION REGISTER

(1588_TX_TIMESTAMP_CONFIG)

This register is used to configure PTP transmit message timestamping.

Note:

Port and GPIO registers share a common address space. Port registers are selected by the Bank Select

(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL).

Offset:

15Ch

Size:

32 bits

Bank:

Bits

Description

Type

Default

31:24

TX PTP Domain (TX_PTP_DOMAIN[7:0])

This field specifies the PTP domain in use. If TX PTP Domain Match Enable

(TX_PTP_DOMAIN_EN) is set, the domainNumber in the PTP message

must match the value in this field in order to recorded the egress time.

Note:

The host S/W must not change this field while the 1588 Enable

(1588_ENABLE) bit in 1588 Command and Control Register

(1588_CMD_CTL) is set.

R/W

00h

TX PTP Domain Match Enable (TX_PTP_DOMAIN_EN)

When this bit is set, the domainNumber in the PTP message is checked

against the value in TX PTP Domain (TX_PTP_DOMAIN[7:0]).

Note:

The host S/W must not change this bit while the 1588 Enable

(1588_ENABLE) bit in 1588 Command and Control Register

(1588_CMD_CTL) is set.

R/W

TX PTP Alternate Master Enable (TX_PTP_ALT_MASTER_EN)

When this bit is set, the alternateMasterFlag in the PTP message is checked

for a zero value.

Note:

The host S/W must not change this bit while the 1588 Enable

(1588_ENABLE) bit in 1588 Command and Control Register

(1588_CMD_CTL) is set.

R/W

TX PTP UDP Checksum Check Disable (TX_PTP_UDP_CHKSUM_DIS)

When this bit is cleared, egress times are not saved if the frame has an

invalid UDP checksum.

When this bit is set, the UDP checksum check is bypassed and the egress

time is saved regardless.

Note:

The host S/W must not change this bit while the 1588 Enable

(1588_ENABLE) bit in 1588 Command and Control Register

(1588_CMD_CTL) is set.

R/W

TX PTP FCS Check Disable (TX_PTP_FCS_DIS)

When this bit is cleared, egress times are not saved if the frame has an

invalid FCS.

When this bit is set, the FCS check is bypassed.

Note:

The host S/W must not change this bit while the 1588 Enable

(1588_ENABLE) bit in 1588 Command and Control Register

(1588_CMD_CTL) is set.

R/W

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