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LAN9250 Datasheet(PDF) 367 Page - Microchip Technology |
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LAN9250 Datasheet(HTML) 367 Page - Microchip Technology |
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367 / 421 page  2015 Microchip Technology Inc. DS00001913A-page 367 LAN9250 14.8.38 1588 PORT TX MODIFICATION REGISTER 2 (1588_TX_MOD2) This register is used to configure TX PTP message modifications. Note: Port and GPIO registers share a common address space. Port registers are selected by the Bank Select (BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL). Offset: 168h Size: 32 bits Bank: 2 Bits Description Type Default 31:1 RESERVED RO - 0 TX PTP Clear UDP/IPv4 Checksum Enable (TX_PTP_CLR_UDPV4_CHKSUM) This bit enables the clearing of the UDP/IPv4 checksum when Pdelay_Resp Message Turnaround Time Insertion or Sync Message Egress Time Insertion is enabled. Note: The host S/W must not change this bit while the 1588 Enable (1588_ENABLE) bit in 1588 Command and Control Register (1588_CMD_CTL) is set. R/W 0b |
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