MCP37231 datasheet(22/144 Pages) MICROCHIP

22 / 144 page

MCP37231/21-200 AND MCP37D31/21-200

DS20005322D-page 22

 2014-2016 Microchip Technology Inc.

Notes:

This 1.8V digital supply voltage is used for the digital I/O circuit, including SPI, CMOS and LVDS data output drivers.

Standby Mode: Most of the internal circuits are turned off, except the internal reference, clock, bias circuits and

SPI interface.

Shutdown Mode: All circuits including reference and clock are turned off except the SPI interface.

Power dissipation (typical) is calculated by using the following equation:

(a) During operation:

PDISS = VDD18 x (IDD_A18 + IDD_D18) + VDD12 x (IDD_A12 + IDD_D12), where IDD_D18 is the digital I/O current for

LVDS or CMOS output. VDD18 = 1.8V and VDD12 = 1.2V are used for typical value calculation.

(b) During Standby mode:

PDISS_STANDBY = (ISTANDBY_AN + ISTANDBY_DIG) x 1.2V

PDISS_SHDN = IDD_SHDN x 1.2V

This parameter is ensured by design, but not 100% tested in production.

This parameter is ensured by characterization, but not 100% tested in production.

See Table 4-2 for details.

Differential reference voltage output at REF1+/- and REF0+/- pins. VREF1 = VREF1+– VREF1-.

VREF0 = VREF0+– VREF0-. These references should not be driven.

Input capacitance refers to the effective capacitance between one differential input pin pair.

10. Channel cross-talk is measured when AIN = -1 dBFS at 12 MHz is applied on one channel while other channel(s)

are terminated with 50

. See Figure 3-39 for details.

11. The ADC core conversion rate. In multi-channel mode, the conversion rate of an individual channel is fS/N, where

N is the number of input channels used.

12. See Figure 4-8 for the details of the clock input circuit.

13. ENOB = (SINAD - 1.76)/6.02.

14. This leakage current is due to the internal pull-up resistor.

15. Dynamic performance is characterized with CH(n)_DIG_GAIN<7:0> = 0011-1000.

Digital Data Output (LVDS Mode)(5)

LVDS High-Level

Differential Output Voltage

VH_LVDS

200

300

400

100

 differential termination,

LVDS bias = 3.5 mA

LVDS Low-Level

Differential Output Voltage

VL_LVDS

-400

-300

-200

100

 differential termination,

LVDS bias = 3.5 mA

LVDS Common-Mode

Voltage

VCM_LVDS

11.15

1.4

Output Capacitance

CINT_LVDS

—

Internal capacitance from

output pin to GND

Differential Load

Resistance (LVDS)

RLVDS

—

100

—



Across LVDS output pairs

Input Leakage Current on Digital I/O Pins

Data Output Pins

ILI_DH

——

µA

VIH = DVDD18

ILI_DL

-1

—

µA

VIL = GND

I/O Pins except Data

Output Pins

ILI_DH

——

µA

VIH = DVDD18

ILI_DL

-35

—

µA

VIL = GND

(14)

TABLE 2-1:

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, AVDD18 =DVDD18 =1.8V,

AVDD12 =DVDD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with

amplitude of -1 dBFS, fIN = 70 MHz, Clock Input = 200 MHz, fS = 200 Msps (ADC Core), Resolution = 16-bit, PLL and decimation

filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100

termination, LVDS driver current setting = 3.5 mA, +25°C is

applied for typical value.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

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