MCP37231 datasheet(98/144 Pages) MICROCHIP

98 / 144 page

 2014-2016 Microchip Technology Inc.

DS20005322D-page 98

MCP37231/21-200 AND MCP37D31/21-200

ADDRESS 0X64 – OUTPUT CLOCK PHASE CONTROL WHEN DECIMATION FILTER IS USED

R/W-0

R/W-1

EN_PHDLY

DCLK_PHDLY_DEC<2:0>

FCB<3:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

EN_PHDLY: Enable digital output clock phase delay control when DLL or decimation filter is used.

Enabled

Disabled (Default)

bit 6-4

DCLK_PHDLY_DEC<2:0>: Digital output clock phase delay control when decimation filter is used(2)

111

= +315° phase-shifted from default(2)

110

= +270° phase-shifted from default

101

= +225° phase-shifted from default(2)

100

= +180° phase-shifted from default

011

= +135° phase-shifted from default(2)

010

= +90° phase-shifted from default

001

= +45° phase-shifted from default(2)

000

= Default(3)

bit 3-0

FCB<3:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.

Note

These bits have an effect only if EN_PHDLY = 1. See Address 0x52 (Register 5-7) for the same feature when DLL is used.

Only available when the decimation filter setting is greater than 2. When FIR_A/B <8:1> = 0’s (default) and FIR_A<6> = 0, only 4-

phase shifts are available (+45°, +135°, +225°, +315°) from default. See Addresses 0x7A, 0x7B and 0x7C (Registers 5-34 – 5-36).

See Addresses 0x6D and 0x52 (Registers 5-28 and 5-7) for DCLK phase shift for other modes.

The phase delay for all other settings is referenced to this default phase.

ADDRESS 0X65 – LVDS OUTPUT POLARITY CONTROL

R/W-0

POL_LVDS<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-0

POL_LVDS<7:0>: Control polarity of LVDS data pairs (Q7+/Q7- – Q0+/Q0-)(1)

1111-1111

= Invert all LVDS pairs

1111-1110

= Invert all LVDS pairs except the LSb pair

• • •

1000-0000

= Invert MSb LVDS pair

• • •

0000-0001

= Invert LSb LVDS pair

0000-0000

= No inversion of LVDS bit pairs (Default)

Note

(a) 14-bit mode: The LSb bit has no effect. (b) 12-bit mode: The last two LSb bits have no effect.

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