MCP37231 datasheet(88/144 Pages) MICROCHIP

88 / 144 page

 2014-2016 Microchip Technology Inc.

DS20005322D-page 88

MCP37231/21-200 AND MCP37D31/21-200

ADDRESS 0X52 – DLL CONTROL

ADDRESS 0X1E – AUTOCAL TIME DELAY CONTROL(1)

R/W-1

R/W-0

AUTOCAL_TIMEDLY<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-0

AUTOCAL_TIMEDLY<7:0>: Auto-calibration start time delay control bits

1111-1111

= Maximum value

• • •

1000-0000

= (Default)

• • •

0000-0000

= Minimum value

Note

EN_AUTOCAL_TIMEDLY in Address 0x07 (Register 5-5) enables this register setting. This register controls the time delay

before the auto-calibration starts. The value increases linearly with the bit settings, from minimum to maximum values.

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

EN_DUTY

DCLK_PHDLY_DLL<2:0>

EN_DLL_DCLK

EN_DLL

EN_CLK

RESET_DLL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

EN_DUTY: Enable DLL circuit for duty cycle correction (DCC) of input clock

1 =

Correction is ON

0 =

Correction is OFF (Default)

bit 6-4

DCLK_PHDLY_DLL<2:0>: Select the phase delay of the digital clock output when using DLL(1)

111 = +315° phase-shifted from default

110 = +270° phase-shifted from default

101 = +225° phase-shifted from default

100 = +180° phase-shifted from default

011 = +135 phase-shifted from default

010 = +90° phase-shifted from default

001 = +45° phase-shifted from default

000 = (Default)

bit 3

EN_DLL_DCLK: Enable DLL digital clock output

Enabled (Default)

Disabled: DLL digital clock is turned off. ADC output is not available when DLL is used.

bit 2

EN_DLL: Enable DLL circuitry to provide a selectable phase clock to digital output clock.

Enabled

Disabled. DLL block is disabled (Default)

bit 1

EN_CLK: Enable clock input buffer

Enabled (Default).

Disabled. No clock is available to the internal circuits, ADC output is not available.

bit 0

RESET_DLL: DLL circuit reset control(2)

DLL is active

DLL circuit is held in reset (Default)

Note

These bits have an effect only if EN_PHDLY = 1 and decimation is not used.

DLL reset control procedure: Set this bit to ‘0’ (reset) and then to ‘1’.

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