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MCP37231 Datasheet(PDF) 76 Page - Microchip Technology

Part # MCP37231
Description  Power-Saving Modes
PDF  144 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP37231 Datasheet(HTML) 76 Page - Microchip Technology

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MCP37231/21-200 AND MCP37D31/21-200
DS20005322D-page 76
 2014-2016 Microchip Technology Inc.
4.15
AutoSync Mode: Synchronizing
Multiple ADCs at the same Clock
using Master and Slave
Configuration
AutoSync allows multiple devices to sample input syn-
chronously at the same clock, and output the conver-
sion data at the same time if they are using the same
digital signal post-processing. Figure 4-27 shows the
system configuration using the AutoSync feature.
Three examples with timing diagram are shown in
Figure 2-9
– Figure 2-11.
Once the devices are synchronized, each device
performs internal calibration (
TPCAL) before sending out
valid data output. Any ADC data output before the
calibration is complete should be ignored.
Note that the calibration time varies slightly from
device to device, and the internal calibration status can
be monitored using the CAL pin or ADC_CAL_STAT bit
in the Register Address 0xC0.
The valid synchronized output is available when all
devices complete their own internal calibration. For
this reason, the user has two options for the
synchronized output: (a) monitor the calibration status
of individual devices and wait until all devices
complete calibrations or (b) use an external AND gate
as shown in Figure 4-26. Master and all Slave devices
are synchronized when the AND gate output toggles
to “High”.
The AutoSync feature can be used with the following
steps:
• Master device is selected by setting SLAVE pin to
“GND”: SYNC pin becomes output pin.
• Slave device is selected by setting SLAVE pin to
“High” (or tie to DVDD): SYNC pin becomes input
pin.
• Feed the Master’s SYNC pin output to Slave’s
SYNC pin.
• Use AutoSync mode using (a) Power-On Reset
(Figure 2-9), (b) RESET Pin (Figure 2-10), or (c)
SOFT RESET bit (Figure 2-11).



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