MCP37231 datasheet(12/144 Pages) MICROCHIP

12 / 144 page

MCP37231/21-200 AND MCP37D31/21-200

DS20005322D-page 12

 2014-2016 Microchip Technology Inc.

TABLE 1-2:

PIN FUNCTION TABLE FOR TFBGA-121

Ball No.

Name

I/O Type

Description

SDIO

Digital Input/

Output

SPI data input/output

VCM

Analog

Output

Common-mode output voltage (900 mV) for analog input signal

Connect a decoupling capacitor (0.1 µF)(1)

REF1+

Differential reference voltage 1 (+/-). Decoupling capacitors are embedded in

the TFBGA package. Leave these pins floating.

REF1-

VBG

Internal bandgap output voltage

A decoupling capacitor (2.2 μF) is embedded in the TFBGA package. Leave

this pin floating.

REF0+

Differential reference 0 (+/-) voltage. Decoupling capacitors are embedded in

the TFBGA package. Leave these pins floating.

REF0-

GND

Supply

Common ground for analog and digital sections

A10

AIN4-

Analog Input Channel 4 differential analog input (-)

A11

AIN2+

Channel 2 differential analog input (+)

SCLK

Digital Input SPI serial clock input

SPI Chip Select input

GND

Supply

Common ground for analog and digital sections

SENSE

Analog

Input

Analog input range selection. See Table 4-2 for SENSE voltage settings.

AVDD12

Supply

Supply voltage input (1.2V) for analog section

AVDD18

Supply voltage input (1.8V) for analog section

B10

AIN4+

Analog Input

Channel 4 differential analog input (+)

B11

AIN2-

Channel 2 differential analog input (-)

WCK/OVR-

(WCK)

Digital

Output

WCK: Word clock sync digital output

OVR: Input overrange indication digital output(2)

WCK/OVR+

(OVR)

GND

Supply

Common ground for analog and digital sections

AVDD12

Supply voltage input (1.2V) for analog section

GND

Common ground pin for analog and digital sections

C10

AIN6-

Analog Input

Channel 6 differential analog input (-)

C11

AIN0+

Channel 0 differential analog input (+)

Q14/Q7-

Digital

Output

Digital data output(3)

CMOS = Q14

DDR LVDS = Q7- (Even bit first), Q15- (MSb byte first)

Serialized LVDS = Q- for the first selected channel (n = 1)

Q15/Q7+

Digital data output(3)

CMOS = Q15

DDR LVDS = Q7+ (Even bit first), Q15+ (MSb byte first)

Serialized LVDS = Q+ for the first selected channel (n = 1)

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