MCP37231 datasheet(96/144 Pages) MICROCHIP

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 2014-2016 Microchip Technology Inc.

DS20005322D-page 96

MCP37231/21-200 AND MCP37D31/21-200

ADDRESS 0X62 – OUTPUT DATA FORMAT AND OUTPUT TEST PATTERN

U-0

R/W-0

R/W-1

R/W-0

—

LVDS_8CH

DATA_FORMAT

OUTPUT_MODE<1:0>

TEST_PATTERNS<2:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented: Not used.

bit 6

LVDS_8CH: LVDS data stream type selection for octal-channel mode(1)

Serialized data stream(2)

Interleaved with parallel data stream(3)(Default)

bit 5

DATA_FORMAT: Output data format selection

Offset binary (unsigned)

Two’s complement (Default)

bit 4-3

OUTPUT_MODE<1:0>: Output mode selection(4)

= DDR LVDS output mode with MSb byte first(5)

= DDR LVDS output mode with even bit first(6)(Default)

= CMOS output mode

= Output disabled

bit 2-0

TEST_PATTERNS<2:0>: Test output data pattern selection

111

= Output data is pseudo-random number (PN) sequence(7)

110

= Sync Pattern for LVDS output.

18-bit mode: '11111111 00000000 10'

16-bit mode: '11111111 00000000'

14-bit mode: '11111111 000000'

12-bit mode: '11111111 0000'

10-bit mode: '11111111 00'

101

= Alternating Sequence for LVDS mode

16-bit mode: ‘01010101 10101010’

14-bit mode: ‘01010101 101010’

100

= Alternating Sequence for CMOS.

Output: ‘11111111 11111111’ alternating with ‘00000000 00000000’

011

= Alternating Sequence for CMOS.

Output: ‘01010101 01010101’ alternating with ‘10101010 10101010’

010

= Ramp Pattern. Output is incremented by:

18-bit mode: 1 LSb per clock cycle

16-bit mode: 1 LSb per 4 clock cycles

14-bit mode: 1 LSb per 16 clock cycles

001

= Double Custom Patterns.

Output: Alternating custom pattern A (see Addresses 0X74 – 0X75 - Registers 5-29 – 5-30) and custom

pattern B (see Address 0X76 - 0X77 - Registers 5-31 – 5-32)(8)

000

= Normal Operation. Output: ADC data (Default)

Note

This bit setting is valid for the octal-channel mode only. See Addresses 0x7D-0x7F (Registers 5-37

– 5-39) for channel order selection.

Serialized LVDS is available in octal-channel with 16-bit mode only: Each LVDS output pair holds a single input channel's data

and outputs in a serial data stream (synchronized with WCK): Q7+/Q7- is for the first channel’s selected data, and Q0+/Q0- is for

the last channel’s selected data. This bit function is enabled only when EN_DSPP_8 = 1 in Address 0x81 (Register 5-41). See

Figure 2-4 for the timing diagram.

The output is in parallel data stream. The first sampled data bit is clocked out first in parallel LVDS output pins, followed by the

next sampled channel data bit. See Figures 2-2 and2-3 for the timing diagram.

See Figures 2-1 – 2-4 for the timing diagram.

Only 16-bit mode is available for this option.

Rising edge: Q15 - Q8.

Falling edge: Q7 - Q0

Rising edge: Q14, Q12, Q10,.... Q0.

Falling edge: Q15, Q13, Q11,... Q1.

Pseudo-random number (PN) code is generated by the linear feedback shift register (LFSR).

The alternating patterns A and B are applied to Q<15:0>. Pattern A<15:14> and Pattern B<15:14> are also applied to OVR and

WCK pins, respectively. Pattern A<1:0> and Pattern B<1:0> are also applied to DM1/DM+ and DM2/DM-.

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