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MCP37231 Datasheet(PDF) 80 Page - Microchip Technology |
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MCP37231 Datasheet(HTML) 80 Page - Microchip Technology |
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80 / 144 page  TABLE 5-3: REGISTER MAP TABLE Addr. Register Name Bits Default Value b7 b6 b5 b4 b3 b2 b1 b0 0x00 SPI Bit Ordering and ADC Mode Selection SHUTDOWN LSb-FIRST SOFT_RESET STANDBY STANDBY SOFT_RESET LSb-FIRST SHUTDOWN 0x24 1 = Shutdown 1 =LSb first 0 =MSb first 0 = Soft Reset 1 = Standby 1 = Standby 0=Soft Reset 1 = LSb first 0 = MSb first 1 =Shutdown 0x01 No. of Channel Selection and Independency Control of Output Data and Clock Divider EN_DATCLK_IND FCB<3> = 0 SEL_NCH<2:0> FCB<2:0> = 111 0x0F 0x02 Output Data and Clock Rate Control OUT_DATARATE<3:0> OUT_CLKRATE<3:0> 0x00 0x04 SPI SDO Timing Control SDO_TIME FCB<6:0> = 0011111 0x9F 0x07 Output Randomizer and WCK Polarity Control POL_WCK EN_AUTOCAL_ TIMEDLY FCB<4:0> = 10001 EN_OUT_ RANDOM 0x62 0x1E Auto-Calibration Time Delay Control AUTOCAL_TIMEDLY<7:0> 0x80 0x52 DLL Control EN_DUTY DCLK_PHDLY_DLL<2:0> EN_DLL_DCLK EN_DLL EN_CLK RESET_DLL 0x0A 0x53 Clock Source Selection FCB<6:4>= 010 CLK_SOURCE FCB<3:0>= 0101 0x45 0x54 PLL Reference Divider PLL_REFDIV<7:0> 0x00 0x55 PLL Output and Reference Divider PLL_OUTDIV<3:0> FCB<1:0> = 10 PLL_REFDIV<9:8> 0x48 0x56 PLL Prescaler (LSb) PLL_PRE (LSB)<7:0> 0x78 0x57 PLL Prescaler (MSb) FCB<3:0> = 0100 PLL_PRE (MSB)<11:8> 0x40 0x58 PLL Charge Pump FCB<2:0> = 000 PLL_BIAS PLL_CHAGPUMP<3:0> 0x12 0x59 PLL Enable Control 1 U FCB<4:3> = 10 EN_PLL_REFDIV FCB<2:1> = 00 EN_PLL FCB<0> = 1 0x41 0x5A PLL Loop Filter Resistor U FCB<1:0> = 01 PLL_RES<4:0> 0x2F 0x5B PLL Loop Filter Cap3 U FCB<1:0> = 01 PLL_CAP3<4:0> 0x27 0x5C PLL Loop Filter Cap1 U FCB<1:0> = 01 PLL_CAP1<4:0> 0x27 0x5D PLL Loop Filter Cap2 U FCB<1:0> = 01 PLL_CAP2<4:0> 0x27 0x5F PLL Enable Control 2 FCB<5:2> = 1111 EN_PLL_OUT EN_PLL_BIAS FCB<1:0> = 01 0xF1 0x62 Output Data Format and Output Test Pattern U LVDS_8CH DATA_FORMAT OUTPUT_MODE<1:0> TEST_PATTERNS<2:0> 0x10 0x63 ADC Output Bits (Resolution) and LVDS Output Load OUTPUT_BIT<3:0> LVDS_LOAD LVDS_IMODE<2:0> 0x01 0x64 Output Clock Phase Control when Decimation Filter is used EN_PHDLY DCLK_PHDLY_DEC<2:0> FCB<3:0> = 0011 0x03 0x65 LVDS Output Polarity Control POL_LVDS<7:0> 0x00 Legend: U = Unimplemented bit, read as ‘0’ FCB = Factory-Controlled Bits. Do not program 1 = bit is set 0 = bit is cleared x = bit is unknown 2: Read-only register. Preprogrammed at the factory for internal use. |
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