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MCP37231 Datasheet(PDF) 101 Page - Microchip Technology |
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MCP37231 Datasheet(HTML) 101 Page - Microchip Technology |
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101 / 144 page ![]() MCP37231/21-200 AND MCP37D31/21-200 DS20005322D-page 101 2014-2016 Microchip Technology Inc. REGISTER 5-27: ADDRESS 0X6B – PLL CALIBRATION R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 FCB<6:2> PLL_CAL_TRIG FCB<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 FCB<6:2>: Factory-Controlled Bits. This is not for the user. Do not change default settings. bit 2 PLL_CAL_TRIG: Manually force recalibration of the PLL at the state of bit transition(1) Toggle from “1” to “0”, or “0” to “1” = Start PLL calibration bit 1-0 FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not program. Note 1: See PLL_CAL_STAT in Address 0xD1 (Register 5-80) for calibration status indication. REGISTER 5-28: ADDRESS 0X6D – PLL OUTPUT AND OUTPUT CLOCK PHASE(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ─ EN_PLL_CLK FCB<1> DCLK_DLY_PLL<2:0> FCB<0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Not used bit 5 EN_PLL_CLK: Enable PLL output clock 1 = PLL output clock is enabled to the ADC core 0 = PLL clock output is disabled (Default) bit 4 FCB<1>: Factory-Controlled Bit. This is not for the user. Do not change default settings. bit 3-1 DCLK_DLY_PLL<2:0>: Output clock is delayed by the number of VCO clock cycles from the nominal PLL output(2) 111 = Delay of 15 cycles 110 = Delay of 14 cycles • • • 001 = Delay of one cycle 000 = No delay (Default) bit 0 FCB<0>: Factory-Controlled Bit. This is not for the user. Do not change default setting. Note 1: This register has effect only when the PLL clock is selected by the CLK_SOURCE bit in Address 0x53 (Register 5-8) and PLL circuit is enabled by EN_PLL bit in Address 0x59 (Register 5-14). 2: This bit setting enables the output clock phase delay. This phase delay control option is applicable when PLL is used as the clock source and the decimation is not used. |
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