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DS26401 Datasheet(PDF) 183 Page - Dallas Semiconductor

Part # DS26401
Description  Octal T1/E1/J1 Framer
PDF  309 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS26401 Datasheet(HTML) 183 Page - Dallas Semiconductor

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DS26401 Octal T1/E1/J1 Framer
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10.10.4 Signaling Debounce
When signaling integration is enabled the signaling data at RSIG is automatically debounced. Signaling must be
constant for three multiframes before being up-dated at RSIG. Signaling debounce is enabled on a global basis.
10.10.5 Receive Signaling Reinsertion at RSER
In this mode, the user will provide a multiframe sync at the RSYNC pin and the signaling data will be reinserted
based on this alignment. In T1 mode, this results in two copies of the signaling data in the RSER data stream. The
original signaling data based on the Fs/ESF frame positions and the realigned data based on the user supplied
multiframe sync applied at RSYNC. In voice channels this extra copy of signaling data is of little consequence. Re-
insertion can be avoided in data channels since this feature is activated on a per-channel basis. For reinsertion, the
elastic store must be enabled, however, the backplane clock can be either 1.544MHz or 2.048MHz.
Signaling reinsertion mode is enabled, on a per-channel basis by setting the Receive Signaling Re-insertion
Channel Select bit high in the RSI register. The channels that are to have signaling reinserted are selected by
writing to the RSI1-RSI4 registers. In E1 mode, the user will generally select all channels or none for reinsertion.
10.10.6 Receive Signaling Freeze
The signaling data in the four multiframe signaling buffer will be frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or change of frame alignment. To allow this freeze action to occur, the
RSFE control bit (RSIGC.1) should be set high. The user can force a freeze by setting the RSFF control bit
(RSIGC.2) high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The four multiframe
buffer provides a three multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER pin if
Receive Signaling Reinsertion is enabled). When freezing is enabled (RSFE = 1), the signaling data will be held in
the last known good state until the corrupting error condition subsides. When the error condition subsides, the
signaling data will be held in the old state for at least an additional 6ms before being allowed to be updated with new
signaling data.



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