DS26401 datasheet(182/309 Pages) DALLAS

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DS26401 Octal T1/E1/J1 Framer

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10.10 E1 Receive Signaling Operation

There are two methods to access receive signaling data—processor-based (i.e., software-based) or hardware

based. Processor-based refers to access through the transmit and receive signaling registers, RS1–RS16.

Hardware-based refers to the RSIG pin. Both methods can be used simultaneously.

10.10.1 Processor-Based Signaling

Signaling data is sampled in the receive data stream and copied into the receive signaling registers, RS1 through

RS16.. The signaling information in these registers is always updated on multiframe boundaries. This function is

always enabled.

10.10.2 Change Of State

In order to avoid constantly monitoring of the receive signaling registers the DS26401 can be programmed to alert

the host when any specific channel or channels undergo a change of their signaling state. RSCSE1 through

RSCSE4 for E1 are used to select which channels can cause a change of state indication. The change of state is

indicated in Latched Status Register 4 (RLS4.3). If signaling integration is enabled then the new signaling state

must be constant for 3 multiframes before a change of state indication is indicated. The user can enable the INT pin

to toggle low upon detection of a change in signaling by setting the appropriate interrupt mask bit RIM4.3. The

signaling integration mode is global and cannot be enabled on a channel-by-channel basis.

The user can identity which channels have undergone a signaling change of state by reading the Receive Signaling

Status (RSS1 through RSS4) registers. The information from these registers tell the user which RSx register to read

for the new signaling data. All changes are indicated in the RSS1–RSS4 registers regardless of the RSCSE1–

RSCSE4 registers.

10.10.3 Hardware-Based Receive Signaling

In hardware based signaling the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a

signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The E1 TS16 signaling data

is still present in the original data stream at RSER. The signaling buffer provides signaling data to the RSIG pin and

also allows signaling data to be re-inserted into the original data stream in a different alignment that is determined

by a multiframe signal from the RSYNC pin. In this mode, the receive elastic store may be enabled or disabled. If

the receive elastic store is enabled, then the backplane clock (RSYSCLK) can be either 1.544 MHz or 2.048MHz. If

IBO mode is enabled then RSYSCLK may also be 4.096MHz, 8.192MHz, or 16.384MHz. The ABCD signaling bits

are output on RSIG in the lower nibble of each channel. The RSIG data is updated once per CAS multiframe (2ms)

unless a freeze is in effect. See the timing diagrams in Section 13.4 for some examples.

DS26401 Datasheet(PDF) 182 Page - Dallas Semiconductor