DS26401 datasheet(185/309 Pages) DALLAS

185 / 309 page

DS26401 Octal T1/E1/J1 Framer

185

RS1 to RS16

Receive Signaling Registers

040h to 04Fh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8]

The Receive Signaling Registers are frozen and not updated during a loss of sync condition.They contain the most

recent signaling information before the LOF occurred.

(MSB)

(LSB)

RS1

CH1-A

CH1-B

CH1-C

CH1-D

CH16-A

CH16-B

CH16-C

CH16-D

RS2

CH2-A

CH2-B

CH2-C

CH2-D

CH17-A

CH17-B

CH17-C

CH17-D

RS3

CH3-A

CH3-B

CH3-C

CH3-D

CH18-A

CH18-B

CH18-C

CH18-D

RS4

CH4-A

CH4-B

CH4-C

CH4-D

CH19-A

CH19-B

CH19-C

CH19-D

RS5

CH5-A

CH5-B

CH5-C

CH5-D

CH20-A

CH20-B

CH20-C

CH20-D

RS6

CH6-A

CH6-B

CH6-C

CH6-D

CH21-A

CH21-B

CH21-C

CH21-D

RS7

CH7-A

CH7-B

CH7-C

CH7-D

CH22-A

CH22-B

CH22-C

CH22-D

RS8

CH8-A

CH8-B

CH8-C

CH8-D

CH23-A

CH23-B

CH23-C

CH23-D

RS9

CH9-A

CH9-B

CH9-C

CH9-D

CH24-A

CH24-B

CH24-C

CH24-D

RS10

CH10-A

CH10-B

CH10-C

CH10-D

CH25-A

CH25-B

CH25-C

CH25-D

RS11

CH11-A

CH11-B

CH11-C

CH11-D

CH26-A

CH26-B

CH26-C

CH26-D

RS12

CH12-A

CH12-B

CH12-C

CH12-D

CH27-A

CH27-B

CH27-C

CH27-D

RS13

CH13-A

CH13-B

CH13-C

CH13-D

CH28-A

CH28-B

CH28-C

CH28-D

RS14

CH14-A

CH14-B

CH14-C

CH14-D

CH29-A

CH29-B

CH29-C

CH29-D

RS15

CH15-A

CH15-B

CH15-C

CH15-D

CH30-A

CH30-B

CH30-C

CH30-D

RS16

RSS1, RSS2, RSS3, RSS4

Receive Signaling Status Registers

098h, 099h, 09Ah, 09ABh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8]

When a channel’s signaling data changes state, the respective bit in registers RSS1-RSS4 will be set and latched.

The RSCOS bit (RLSR4.3) will be set if the channel was also enabled by setting the appropriate bit in RSCSE1-4.

The INT signal will go low if enabled by the interrupt mask bit RIM4.3. The bit will remain set until read. Note that in

CAS mode, the LSB of RSS1 would typically represent the CAS alignment bits, and the LSB of RSS3 represents

reserved bits and the distant multiframe alarm.

(MSB)

(LSB)

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1*

RSS1

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

RSS2

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17*

RSS3

CH32

CH31

CH30

CH29

CH28

CH27

CH26

CH25

RSS4

Status bits in this register are latched.

DS26401 Datasheet(PDF) 185 Page - Dallas Semiconductor

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