DS26401 datasheet(188/309 Pages) DALLAS

188 / 309 page

DS26401 Octal T1/E1/J1 Framer

188

10.12 Receive Channel Blocking Operation

The Receive Channel blocking Registers (RCBR1 / RCBR2 / RCBR3 / RCBR4) and the Transmit Channel Blocking

Registers (TCBR1 / TCBR2 / TCBR3 / TCBR4) control the RCHBLK and TCHBLK pins respectively. The RCHBLK

and TCHBLK pins are user programmable outputs that can be forced high or low during individual channels. These

outputs can be used to block clocks to a USART or LAPD controller in ISDN–PRI applications. When the

appropriate bits are set to a one, the RCHBLK and TCHBLK pin will be held high during the entire corresponding

channel time.

RCBR1, RCBR2, RCBR3, RCBR4

Receive Channel Blocking Registers

0C4h, 0C5h, 0C6h, 0C7h [+ (200h x n) : where n = 0 to 7, for Ports

1 to 8]

(MSB)

(LSB)

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

RCBR1

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

RCBR2

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

RCBR3

CH32

CH31

CH30

CH29

CH28

CH27

CH26

CH25

RCBR4

Bits 0 to 7 / Receive Channels 1 to 32 Channel Blocking Control Bits (CH1 to CH32)

0 = force the RCHBLK pin to remain low during this channel time

1 = force the RCHBLK pin high during this channel time

DS26401 Datasheet(PDF) 188 Page - Dallas Semiconductor

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