DS26401 datasheet(192/309 Pages) DALLAS

192 / 309 page

DS26401 Octal T1/E1/J1 Framer

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10.13.2 Additional E1 Receive Elastic Store Information

If the receive side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the

RSYSCLK pin. For higher rate system clock applications, see the Interleave Bus Option section. The user has the

option of either providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin provide a pulse on

frame/multiframe boundaries. If Signaling Reinsertion is enabled, signaling data in TS16 is re-aligned to the

multiframe sync input on RSYNC. Otherwise, a multiframe sync input on RSYNC is treated as a simple frame

boundary by the elastic store. The framer will always indicate frame boundaries on the network side of the elastic

store via the RFSYNC output whether the elastic store is enabled or not. Multiframe boundaries will always be

indicated via the RMSYNC output. If the elastic store is enabled, then RMSYNC will output the multiframe boundary

on the backplane side of the elastic store. When the device is receiving E1 and the backplane is enabled for

1.544MHz operation, the RMSYNC signal will output the E1 multiframe boundaries as delayed through the elastic

store.

10.13.2.1 Elastic Stores Initialization

There are two elastic store initializations that may be used to improve performance in certain applications, Elastic

Store Reset and Elastic Store Align. Both of these involve the manipulation of the elastic store’s read and write

pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLK,

respectively). The elastic store reset is used to minimize the delay through the elastic store. The elastic store align

bit is used to 'center' the read/write pointers to the extent possible.

Elastic Store Delay After Initialization

INITIALIZATION

BIT

DELAY

Receive Elastic Store Reset

RESCR.2

N bytes < Delay < 1 Frame + N bytes

Transmit Elastic Store Reset

TESCR.2

N bytes < Delay < 1 Frame + N bytes

Receive Elastic Store Align

RESCR.3

1/2 Frame < Delay < 1 1/2 Frames

Transmit Elastic Store Align

TESCR.3

1/2 Frame < Delay < 1 1/2 Frames

N = 9 for RSZS = 0

N = 2 for RSZS = 1

10.13.2.2 Minimum Delay Mode

Elastic store minimum delay mode may be used when the elastic store’s system clock is locked to its network clock

(i.e., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side). RESCR.1

enable the receive elastic store minimum delay mode. When enabled the elastic stores will be forced to a maximum

depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in T1 applications that

interface to a 2.048MHz bus. Certain restrictions apply when minimum delay mode is used. In addition to the

restriction mentioned above, RSYNC must be configured as an output when the receive elastic store is in minimum

delay mode and TSYNC must be configured as an output when transmit minimum delay mode is enabled. In a

typical application RSYSCLK and TSYSCLK are locked to RCLK, and RSYNC (frame output mode) is connected to

TSSYNC (frame input mode). All of the slip contention logic in the framer is disabled (since slips cannot occur). On

power-up after the RSYSCLK and TSYSCLK signals have locked to their respective network clock signals, the

elastic store reset bit (RESCR.2) should be toggled from a zero to a one to ensure proper operation.

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