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DS26401 Datasheet(PDF) 193 Page - Dallas Semiconductor

Part # DS26401
Description  Octal T1/E1/J1 Framer
PDF  309 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS26401 Datasheet(HTML) 193 Page - Dallas Semiconductor

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DS26401 Octal T1/E1/J1 Framer
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10.14 Fractional E1 Support (Gapped Clock Mode)
The DS26401 can be programmed to output gapped clocks for selected channels in the receive and transmit paths
to simplify connections into a USART or LAPD controller in Fractional T1/E1 or ISDN–PRI applications. When the
gapped clock feature is enabled, a gated clock is output on the RCHCLK signal. The channel selection is controlled
via the receive-gapped-clock channel-select registers (RGCCS1–RGCCS4). The receive path is enabled for
gapped clock mode with the RGCLKEN bit (RESCR.6). Both 56kbps and 64kbps channel formats are supported as
determined by RESCR.7. When 56kbps mode is selected, the clock corresponding to the Data/Control bit in the
channel is omitted (only the seven most significant bits of the channel have clocks).
Register Name:
RGCCS1, RGCCS2, RGCCS3, RGCCS4
Register Description:
Receive Gapped Clock Channel Select Registers
Register Address:
0CCh, 0CDh, 0CEh, 0CFh [+ (200h x n) : where n = 0 to 7, for
Ports 1 to 8]
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RGCCS1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RGCCS2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RGCCS3
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
RGCCS4
Bits 0 to 7 / Receive Channels 1 to 32 Gapped Clock Channel Select Bits (CH1 to CH32)
0 = no clock is present on RCHCLK during this channel time
1 = force a clock on RCHCLK during this channel time. The clock will be synchronous with RCLK if the
elastic store is disabled, and synchronous with RSYSCLK if the elastic store is enabled.



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