DS26401 datasheet(194/309 Pages) DALLAS

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DS26401 Octal T1/E1/J1 Framer

194

10.15 Additional Sa-Bit and Si-Bit Receive Operation (E1 Mode)

When operated in the E1 mode the DS21411 receiver provides extended access to both the Sa and the Si bits.

The RAF and RNAF registers will always report the data as it received in the Sa and Si bit locations. The RAF and

RNAF registers are updated on align frame boundaries. The setting of the Receive Align Frame bit in Latched

Status Register 2 (RLS2.0) will indicate that the contents of the RAF and RNAF have been updated. The host can

use the RLS2.0 bit to know when to read the RAF and RNAF registers. The host has 250

ms to retrieve the data

before it is lost.

Also there are eight registers (RsiAF, RSiNAF, RRA, Rsa4 to Rsa8) that report the Si and Sa bits as they are

received. These registers are updated with the setting of the Receive CRC4 Multiframe bit in Latched Status

retrieve the data before it is lost. Please see the register descriptions below for additional information.

RAF

Receive Align Frame Register

064h + (200h x n) : where n = 0 to 7, for Ports 1 to 8

Bit #

Name

Default

Bit 0 / Frame Alignment Signal Bit (1)

Bit 1 / Frame Alignment Signal Bit (1)

Bit 2 / Frame Alignment Signal Bit (0)

Bit 3 / Frame Alignment Signal Bit (1)

Bit 4 / Frame Alignment Signal Bit (1)

Bit 5 / Frame Alignment Signal Bit (0)

Bit 6 / Frame Alignment Signal Bit (0)

Bit 7 / International Bit (Si)

DS26401 Datasheet(PDF) 194 Page - Dallas Semiconductor