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DS26401 Datasheet(PDF) 207 Page - Dallas Semiconductor |
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DS26401 Datasheet(HTML) 207 Page - Dallas Semiconductor |
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207 / 309 page  DS26401 Octal T1/E1/J1 Framer 207 HDLC Receive Example The HDLC status registers in the DS26401 allow for flexible software interface to meet the user’s preferences. When receiving HDLC messages, the host can chose to be interrupt driven, or to poll to desired status registers, or a combination of polling and interrupt processes may be used. An example routine for using the DS26401 HDLC receiver is given in Figure 10-3. Figure 10-3. Receive HDLC Example Reset Receive HDLC Controller (RHC.6) Configure Receive HDLC Controller (RHC, RHBSE, RHFC) Start New Message Buffer Enable Interrupts RPE and RHWM Start New Message Buffer Interrupt? Read Register RHPBA Read N Bytes From Rx HDLC FIFO (RHF) N = RHPBA[5..0] MS = 0? (MS = RHPBA[7]) NO YES NO YES Read RRTS5 for Packet Status (PS2..0) Take appropriate action No Action Required Work Another Process |
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