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DS26401 Datasheet(PDF) 252 Page - Dallas Semiconductor

Part # DS26401
Description  Octal T1/E1/J1 Framer
PDF  309 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS26401 Datasheet(HTML) 252 Page - Dallas Semiconductor

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DS26401 Octal T1/E1/J1 Framer
252
Register Name:
TLS2
Register Description:
Transmit Latched Status Register 2 (HDLC)
Register Address:
191h + (200h x n) : where n = 0 to 7, for Ports 1 to 8
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
TUDR
TMEND
TLWMS
TNFS
Default
0
0
0
0
0
0
0
0
All bits in this register are latched and can create interrupts.
Bit 0 / Transmit FIFO Not Full Set Condition (TNFS).
Set when the transmit 64-byte FIFO has at least one empty
byte available for write. Rising edge detect of TNF. Indicates change of state from full to not full.
Bit 1 / Transmit FIFO Below Low-Watermark Set Condition (TLWMS).
Set when the transmit 64-byte FIFO
empties beyond the low watermark as defined by the Transmit Low-Watermark bits (TLWM) (rising edge detect of
TLWM).
Bit 2 / Transmit Message End Event (TMEND).
Set when the transmit HDLC controller has finished sending a
message.
Bit 3 / Transmit FIFO Underrun Event (TUDR).
Set when the transmit FIFO empties out without having seen the
TMEND bit set. An abort is automatically sent.
Bits 4 to 7 / Unused



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