AD9680 datasheet(38/99 Pages) AD

38 / 99 page

AD9680

Data Sheet

Rev. C | Page 36 of 97

ADC

0.1µF

BALUN

NOTES

1. SEE TABLE 9 FOR COMPONENT VALUES.

Figure 115. Differential Transformer-Coupled Configuration for AD9680

Table 9. Differential Transformer-Coupled Input Configuration Component Values

Device

Frequency Range

Transformer

R1 (Ω)

R2 (Ω)

R3 (Ω)

C1 (pF)

C2 (pF)

AD9680-500

DC to 250 MHz

ETC1-1-13

250 MHz to 2 GHz

BAL-0006/BAL-0006SMG

AD9680-820

DC to 410 MHz

ETC1-1-13

410 MHz to 2 GHz

BAL-0006/BAL-0006SMG

AD9680-1000

DC to 500 MHz

ETC1-1-13/BAL-0006SMG

500 MHz to 2 GHz

BAL-0006/BAL-0006SMG

Open

AD9680-1250

DC to 625 MHz

BAL-0006SMG

625 MHz to 2 GHz

BAL-0006SMG

Open

Input Common Mode

The analog inputs of the AD9680 are internally biased to the

common mode as shown in Figure 116. The common-mode

buffer has a limited range in that the performance suffers greatly

if the common-mode voltage drops by more than 100 mV.

Therefore, in dc-coupled applications, set the common-mode

voltage to 2.05 V, ±100 mV to ensure proper ADC operation.

The full-scale voltage setting must be at a 1.7 V p-p differential

if running in a dc-coupled application.

Analog Input Buffer Controls and SFDR Optimization

The AD9680 input buffer offers flexible controls for the analog

inputs, such as input termination, buffer current, and input full-

scale adjustment. All the available controls are shown in Figure 116.

10pF

VIN+x

VIN–x

AVDD3

VCM

BUFFER

400Ω

AVDD3

1.5pF

3pF

1.5pF

3pF

AIN CONTROL

SPI REGISTERS

(0x008, 0x015,

0x016, 0x018,

0x019, 0x01A,

0x11A, 0x934,

0x935)

Figure 116. Analog Input Controls

Using the 0x018, 0x019, 0x01A, 0x11A, 0x934, and 0x935 registers,

the buffer behavior on each channel can be adjusted to optimize the

SFDR over various input frequencies and bandwidths of interest.

Input Buffer Control Registers (0x018, 0x019, 0x01A,

0x935, 0x934, 0x11A)

The input buffer has many registers that set the bias currents and

other settings for operation at different frequencies. These bias

currents and settings can be changed to suit the input frequency

range of operation. Register 0x018 controls the buffer bias current

to help with the kickback from the ADC core. This setting can be

scaled from a low setting of 1.0× to a high setting of 8.5×. The

default setting is 3.0× for the AD9680-1000 and AD9680-820,

and 2.0× for the AD9680-500. These settings are sufficient for

operation in the first Nyquist zone for the products. When the

input buffer current in Register 0x018 is set, the amount of

current required by the AVDD3 supply changes. This relationship

is shown in Figure 117. For a complete list of buffer current

settings, see Table 36.

BUFFER CONTROL 1 SETTING

1.5×

2.5×

3.5×

4.5×

5.5×

6.5×

7.5×

8.5×

100

150

200

250

300

AD9680-1250,

AD9680-1000,

AND

AD9680-820

AD9680-500

Figure 117. IAVDD3 vs. Buffer Control 1 Setting in Register 0x018

The 0x019, 0x01A, 0x11A, and 0x935 registers offer secondary

bias controls for the input buffer for frequencies >500 MHz.

wider signal bandwidth but may result in slightly lower linearity

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