AD9680 datasheet(74/99 Pages) AD

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AD9680

Data Sheet

Rev. C | Page 72 of 97

Table 27. JESD204B Output Configurations for N΄ = 8

Number of Virtual

Converters Supported

(Same Value as M)

JESD204B Quick

Configuration

(0x570)

Serial Line Rate1

JESD204B Transport Layer Settings2

N΄

0x00

10 × fOUT

7 to 8

0 to 1

Only valid K

values which

are divisible

by 4 are

supported

0x01

10 × fOUT

7 to 8

0 to 1

0x40

5 × fOUT

7 to 8

0 to 1

0x41

5 × fOUT

7 to 8

0 to 1

0x42

5 × fOUT

7 to 8

0 to 1

0x80

2.5 × fOUT

7 to 8

0 to 1

0x81

2.5 × fOUT

7 to 8

0 to 1

0x09

20 × fOUT

7 to 8

0 to 1

0x48

10 × fOUT

7 to 8

0 to 1

0x49

10 × fOUT

7 to 8

0 to 1

0x88

5 × fOUT

7 to 8

0 to 1

0x89

5 × fOUT

7 to 8

0 to 1

0x8A

5 × fOUT

7 to 8

0 to 1

fOUT = output sample rate = ADC sample rate/chip decimation ratio. The JESD204B serial line rate must be ≥3125 Mbps and ≤12,500 Mbps; when the serial line rate is

≤12.5 Gbps and ≥6.25 Gbps, the low line rate mode must be disabled (set Bit 4 to 0x0 in Register 0x56E). When the serial line rate is <6.25 Gbps and ≥3.125 Gbps, the

low line rate mode must be enabled (set Bit 4 to 0x1 in Register 0x56E).

JESD204B transport layer descriptions are as described in the JESD204B Overview section.

For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32.

See the Example 1: Full Bandwidth Mode section and the

Example 2: ADC with DDC Option (Two ADCs Plus Four

DDCs) section for two examples describing which JESD204B

transport layer settings are valid for a given chip mode.

Example 1: Full Bandwidth Mode

Chip application mode = full bandwidth mode (see Figure 169).

•

Two 14-bit converters at 1000 MSPS

•

Full bandwidth application layer mode

•

No decimation

JESD204B output configuration is as follows:

•

Two virtual converters required (see Table 26)

•

Output sample rate (fOUT) = 1000/1 = 1000 MSPS

JESD204B supported output configurations (see Table 26)

include:

•

N΄ = 16 bits

•

N = 14 bits

•

L = 4, M = 2, and F = 1, or L = 4, M = 2, and F = 2 (quick

configuration = 0x88 or 0x89)

•

CS = 0 to 2

•

K = 32

•

Output serial line rate = 10 Gbps per lane, low line rate

mode disabled

JESD204B

TRANSMIT

INTERFACE

FAST

DETECTION

FAST

DETECTION

CMOS

CONVERTER 0

CONVERTER 1

14-BIT

1Gbps

REAL/I

14-BIT

1Gbps

REAL/Q

JESD204B

LANES

AT UP TO

12.5Gbps

Figure 169. Full Bandwidth Mode

Example 2: ADC with DDC Option (Two ADCs Plus Four

DDCs)

Chip application mode = four-DDC mode. (see Figure 170).

•

Two 14-bit converters at 1 GSPS

•

Four DDC application layer mode with complex outputs

(I/Q)

•

Chip decimation ratio = 16

•

DDC decimation ratio = 16 (see Table 15).

JESD204B output configuration is as follows:

•

Virtual converters required = 8 (see Table 26)

•

Output sample rate (fOUT) = 1000/16 = 62.5 MSPS

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